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公开(公告)号：US20230128985A1
公开(公告)日：2023-04-27
申请号：US17508113
申请日：2021-10-22
IPC分类号： H01L23/528 , H01L27/12
摘要： A semiconductor structure and method of manufacturing a semiconductor structure having a front side and an opposing backside. An early power delivery network (EBPDN) of wires is built above a substrate layer. Buried power rails (BPRs) are built above levels of the PDN and connected to the EBPDN by short length via connections that can be self-aligned to the back side buried power rails. Both BPRs and vias connections have a common metallization. A front side level of transistor devices are built at the front side of the structure above the BPRs. The resulting formed buried power rail structure has an aspect ratio of height:width greater than 4:1, a height >3 times a height of the formed via structure; and a via structure having a length greater than a height of the formed conductive power rail structure.
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公开(公告)号：US20230101678A1
公开(公告)日：2023-03-30
申请号：US17485088
申请日：2021-09-24
发明人： Albert Chu , Junli Wang , Brent Anderson
IPC分类号： G06F30/392
摘要： Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.
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公开(公告)号：US20230094757A1
公开(公告)日：2023-03-30
申请号：US17481362
申请日：2021-09-22
发明人： Lawrence A. Clevenger , Brent Anderson , Nicholas Anthony Lanzillo , Christopher J. Penny , Kisik Choi , Robert ROBISON
IPC分类号： H01L21/768 , H01L23/522
摘要： An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.
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公开(公告)号：US20230066614A1
公开(公告)日：2023-03-02
申请号：US17412300
申请日：2021-08-26
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768
摘要： An approach to provide a semiconductor structure using different two metal materials for interconnects in the middle of the line and the back end of the line metal layers of a semiconductor chip. The semiconductor structure includes the first metal material connecting both horizontally and vertically with the second metal material and the second metal material connecting both horizontally and vertically with the first metal material where the second metal material is more resistant to electromigration than the first metal material.
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公开(公告)号：US20230064608A1
公开(公告)日：2023-03-02
申请号：US17465316
申请日：2021-09-02
IPC分类号： H01L29/66 , H01L23/48 , H01L29/08 , H01L29/78 , H01L21/8234
摘要： A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.
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公开(公告)号：US20220399224A1
公开(公告)日：2022-12-15
申请号：US17342650
申请日：2021-06-09
发明人： Ruilong Xie , Takeshi Nogami , Roy R. Yu , Balasubramanian Pranatharthiharan , Albert M. Young , Kisik Choi , Brent Anderson
IPC分类号： H01L21/74 , H01L21/768 , H01L23/535 , H01L23/528
摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.
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公开(公告)号：US11302575B2
公开(公告)日：2022-04-12
申请号：US16941860
申请日：2020-07-29
发明人： Brent Anderson , Christopher J Penny , Lawrence A. Clevenger , Nicholas Anthony Lanzillo , Kisik Choi , Robert Robison
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532
摘要： Interconnect structures having subtractive line with damascene second line type are provided. In one aspect, an interconnect structure includes: first metal lines of a first line type disposed on a substrate; and at least one second metal line of a second line type disposed on the substrate between two of the first metal lines, wherein the first line type includes subtractive lines and the second line type includes damascene lines such that the first metal lines have a different metallization structure from the at least one second metal line. A method of forming an interconnect structure is also provided.
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公开(公告)号：US20220005732A1
公开(公告)日：2022-01-06
申请号：US17479346
申请日：2021-09-20
发明人： Lawrence A. Clevenger , Brent Anderson , Kisik Choi , Nicholas Anthony Lanzillo , Christopher J. Penny , Robert Robison
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.
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公开(公告)号：US20210327751A1
公开(公告)日：2021-10-21
申请号：US16851167
申请日：2020-04-17
发明人： Christopher J. Penny , Brent Anderson , Lawrence A. Clevenger , Robert Robison , Kisik Choi , Nicholas Anthony Lanzillo
IPC分类号： H01L21/768 , H01L23/522
摘要： A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.
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公开(公告)号：US20210305152A1
公开(公告)日：2021-09-30
申请号：US16830550
申请日：2020-03-26
发明人： DANIEL JAMES DECHENE , Craig Michael Child , Lawrence A. Clevenger , Kisik Choi , Brent Anderson
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L23/528
摘要： A multilayered integrated circuit includes a first layer with a first conductive element overlaying a substrate, a second layer with a second conductive element overlaying the first layer, an intermediate layer between the first layer and the second layer, and a via structure. The via structure is partially embedded within the intermediate layer and is communicatively coupled to the first conductive element and the second conductive element. The via structure extends from the first conductive element and has a first end with a first end width and a second end with a second end width. The second end is further from the substrate than the first end and the first end width is greater than the second end width such that the via structure tapers between the first end and the second end of the via structure.
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