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公开(公告)号：US20230099303A1
公开(公告)日：2023-03-30
申请号：US17484649
申请日：2021-09-24
发明人： Dexin Kong , Ashim Dutta , Ekmini Anuja De Silva , Daniel Schmidt
摘要： A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.
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公开(公告)号：US11430513B1
公开(公告)日：2022-08-30
申请号：US17391496
申请日：2021-08-02
发明人： Soon-Cheon Seo , Youngseok Kim , Dexin Kong , Takashi Ando , Hiroyuki Miyazoe
摘要： A low voltage forming NVM structure including a plurality of ReRAM devices arranged in a cross bar array and sandwiched between a plurality of first electrically conductive structures and a plurality of second electrically conductive structures. Each first electrically conductive structure is oriented perpendicular to each second electrically conductive structure. The plurality of second electrically conductive structures includes a first set of second electrically conductive structures having a first top trench area A1, and a second set of second electrically conductive structures having a second top trench area A2 that is greater than A1. Each second electrically conductive structure of the first set contacts a surface of at least one of the first electrically conductive structures, and each second electrically conductive structure of the second set contacts a top electrode of at least one of the ReRAM devices.
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公开(公告)号：US11043634B2
公开(公告)日：2021-06-22
申请号：US16378988
申请日：2019-04-09
发明人： Dexin Kong , Takashi Ando , Kangguo Cheng , Juntao Li
IPC分类号： H01L45/00
摘要： A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.
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公开(公告)号：US11004751B2
公开(公告)日：2021-05-11
申请号：US16284261
申请日：2019-02-25
发明人： Kangguo Cheng , Juntao Li , Dexin Kong , Zhenxing Bi
IPC分类号： H01L21/8234 , H01L21/762 , H01L29/66 , H01L27/088 , H01L21/311 , H01L29/06 , H01L21/308 , H01L21/3065
摘要： A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.
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公开(公告)号：US10903421B2
公开(公告)日：2021-01-26
申请号：US16148510
申请日：2018-10-01
发明人： Dexin Kong , Juntao Li , Takashi Ando , Kangguo Cheng
摘要： A method for manufacturing a semiconductor memory device includes forming a bottom electrode on a bottom contact layer, and forming a dielectric layer covering sides of the bottom electrode. In the method, a switching element layer is deposited on the dielectric layer and the bottom electrode, a top electrode layer is deposited on the switching element layer, and a hardmask layer is deposited on the top electrode layer. The switching element, top electrode and hardmask layers are patterned into a pillar on the bottom electrode. The method further includes forming a spacer layer on the dielectric layer on sides of the pillar, and forming a metal layer on the dielectric layer adjacent the spacer layer and around the pillar.
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公开(公告)号：US10804274B2
公开(公告)日：2020-10-13
申请号：US16286843
申请日：2019-02-27
发明人： Zhenxing Bi , Zheng Xu , Dexin Kong , Kangguo Cheng
IPC分类号： H01L21/44 , H01L27/105 , H01L21/8229 , H01L29/06
摘要： A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.
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7.发明申请公开(公告)号：US20200258779A1
公开(公告)日：2020-08-13
申请号：US16860835
申请日：2020-04-28
发明人： Kangguo Cheng , Juntao Li , Zhenxing Bi , Dexin Kong
IPC分类号： H01L21/768 , H01L23/522
摘要： A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.
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8.发明授权公开(公告)号：US10692203B2
公开(公告)日：2020-06-23
申请号：US15899197
申请日：2018-02-19
发明人： Dexin Kong , Robin Hsin Kuo Chao , Huai Huang
摘要： Techniques for measuring defectivity using model-less scatterometry with cognitive machine learning are provided. In one aspect, a method for defectivity detection includes: capturing SEM images of defects from a plurality of training wafers; classifying type and density of the defects from the SEM images; making training scatterometry scans of a same location on the training wafers as the SEM images; training a machine learning model to correlate the training scatterometry scans with the type and density of the defects from the same location in the SEM images; making scatterometry scans of production wafers; and detecting defectivity in the production wafers by measuring the type and density of the defects in the production wafers using the machine learning model, as trained, and the scatterometry scans of the production wafers. A system for defectivity detection is also provided.
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公开(公告)号：US10586875B2
公开(公告)日：2020-03-10
申请号：US16026880
申请日：2018-07-03
发明人： Zheng Xu , Zhenxing Bi , Dexin Kong , Qianwen Chen
IPC分类号： H01L29/788 , H01L27/11521 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/49 , H01L29/786 , H01L21/28
摘要： A method for fabricating a semiconductor device including a gate-all-around based non-volatile memory device includes forming gate-all-around field effect transistor (GAA FET) channels, depositing tunnel dielectric material around the GAA FET channels to isolate the GAA FET channels, forming a floating gate, including depositing first gate material over the isolated GAA FET channels, and forming at least one control gate, including depositing second gate material over the isolated GAA FET channels.
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10.发明申请公开(公告)号：US20190259145A1
公开(公告)日：2019-08-22
申请号：US15899197
申请日：2018-02-19
发明人： Dexin Kong , Robin Hsin Kuo Chao , Huai Huang
摘要： Techniques for measuring defectivity using model-less scatterometry with cognitive machine learning are provided. In one aspect, a method for defectivity detection includes: capturing SEM images of defects from a plurality of training wafers; classifying type and density of the defects from the SEM images; making training scatterometry scans of a same location on the training wafers as the SEM images; training a machine learning model to correlate the training scatterometry scans with the type and density of the defects from the same location in the SEM images; making scatterometry scans of production wafers; and detecting defectivity in the production wafers by measuring the type and density of the defects in the production wafers using the machine learning model, as trained, and the scatterometry scans of the production wafers. A system for defectivity detection is also provided.
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