Stacked field effect transistor devices with replacement gate

    公开(公告)号:US12094937B2

    公开(公告)日:2024-09-17

    申请号:US17481537

    申请日:2021-09-22

    摘要: A stacked field effect transistor device is provided. The stacked field effect transistor device includes a lower semiconductor channel segment between a first pair of source/drains, and an upper semiconductor channel segment between a second pair of source/drains. The stacked device further includes a gate dielectric layer on the upper and lower semiconductor channel segments, and a first work function material layer on the gate dielectric layer on the lower semiconductor channel segment. The stacked device further includes a first conductive gate fill on the first work function material layer, and a replacement work function material layer on the gate dielectric layer on the upper semiconductor channel segment and the first conductive gate fill, wherein the replacement work function material layer is a different work function material from the first work function material layer. The device further includes a replacement conductive gate fill on the replacement work function material layer.

    Aspect ratio trapping in channel last process

    公开(公告)号:US11309408B2

    公开(公告)日:2022-04-19

    申请号:US16216077

    申请日:2018-12-11

    摘要: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

    Unconfined buried interconnects
    9.
    发明授权

    公开(公告)号:US11183419B2

    公开(公告)日:2021-11-23

    申请号:US16821074

    申请日:2020-03-17

    摘要: Embodiments of the present invention are directed to fabrication methods and resulting semiconductor structures having a bulb-shaped buried interconnect positioned below a shallow trench isolation region. In a non-limiting embodiment of the invention, a cavity is formed below a surface of a substrate. The cavity extends under a portion of a semiconductor fin. The cavity is filled with a sacrificial material and a shallow trench isolation region is formed on the sacrificial material in the cavity. A portion of the shallow trench isolation region is removed to expose a surface of the sacrificial material in the cavity. The sacrificial material is removed from the cavity and replaced with a buried interconnect.

    Capacitor based resistive processing unit with symmetric weight update

    公开(公告)号:US11176451B2

    公开(公告)日:2021-11-16

    申请号:US16159205

    申请日:2018-10-12

    摘要: Systems and methods for a capacitor based resistive processing unit with symmetrical weight updating include a first capacitor that stores a charge corresponding to a weight value. A readout circuit reads the charge stored in the first capacitor to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. An update circuit updates the weight value stored in the first capacitor, including a second capacitor in communication with the first capacitor to transfer an amount of charge to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.