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公开(公告)号:US12101929B2
公开(公告)日:2024-09-24
申请号:US17543235
申请日:2021-12-06
发明人: Effendi Leobandung
IPC分类号: H10B41/27 , H01L21/308 , H01L29/423 , H01L29/51 , H10B41/35 , H10B43/27 , H10B43/35
CPC分类号: H10B41/27 , H01L21/3086 , H01L29/42324 , H01L29/4234 , H01L29/517 , H10B41/35 , H10B43/27 , H10B43/35
摘要: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.
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公开(公告)号:US12094937B2
公开(公告)日:2024-09-17
申请号:US17481537
申请日:2021-09-22
发明人: Effendi Leobandung
IPC分类号: H01L27/092 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号: H01L29/41725 , H01L29/1033 , H01L29/42372 , H01L29/66545
摘要: A stacked field effect transistor device is provided. The stacked field effect transistor device includes a lower semiconductor channel segment between a first pair of source/drains, and an upper semiconductor channel segment between a second pair of source/drains. The stacked device further includes a gate dielectric layer on the upper and lower semiconductor channel segments, and a first work function material layer on the gate dielectric layer on the lower semiconductor channel segment. The stacked device further includes a first conductive gate fill on the first work function material layer, and a replacement work function material layer on the gate dielectric layer on the upper semiconductor channel segment and the first conductive gate fill, wherein the replacement work function material layer is a different work function material from the first work function material layer. The device further includes a replacement conductive gate fill on the replacement work function material layer.
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公开(公告)号:US11894361B2
公开(公告)日:2024-02-06
申请号:US17545501
申请日:2021-12-08
发明人: Julien Frougier , Sagarika Mukesh , Anthony I. Chou , Andrew M. Greene , Ruilong Xie , Veeraraghavan S. Basker , Junli Wang , Effendi Leobandung , Jingyun Zhang , Nicolas Loubet
IPC分类号: H01L27/02 , H01L21/8234 , H01L21/84 , H01L27/12
CPC分类号: H01L27/0255 , H01L21/823481 , H01L21/84 , H01L27/0296 , H01L27/1207 , H01L27/1211
摘要: A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.
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公开(公告)号:US20230354592A1
公开(公告)日:2023-11-02
申请号:US18348572
申请日:2023-07-07
摘要: A semiconductor device is provided. The semiconductor device includes a metal-oxide-semiconductor field-effect-transistor (MOSFET) device electrically attachable to a first data line and a read-only memory (ROM) element. The ROM element is electrically interposable between the MOSFET device and a second data line. The ROM element includes first and second sets of memory cells in high and low resistance states, respectively, to form a secure identifier (ID).
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公开(公告)号:US11789069B2
公开(公告)日:2023-10-17
申请号:US17541708
申请日:2021-12-03
发明人: Effendi Leobandung
IPC分类号: G01R31/28 , G01R31/311 , G06N20/00
CPC分类号: G01R31/311 , G01R31/2853 , G06N20/00
摘要: Embodiments of the invention include a computer-implemented method that includes controlling, using a processor, a high-resolution optical inspection tool (HROIT) to identify a reference die tamper circuit on a reference die of a wafer; and controlling, using the processor, a low-resolution optical inspection tool (LROIT) to use the reference die tamper circuit to determine that the reference die tamper circuit is on a second die of the wafer.
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公开(公告)号:US20220181213A1
公开(公告)日:2022-06-09
申请号:US17678208
申请日:2022-02-23
IPC分类号: H01L21/8234 , H01L29/06 , H01L21/762
摘要: Embodiments of the invention are directed to a transistor that includes a source or drain (S/D) region having an S/D formation assistance region, wherein the S/D formation assistance region includes a top surface, sidewalls, and a bottom surface. The S/D formation assistance region is at least partially within a portion of a substrate. An S/D isolation region is formed around the sidewalls and the bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.
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公开(公告)号:US11309408B2
公开(公告)日:2022-04-19
申请号:US16216077
申请日:2018-12-11
发明人: Effendi Leobandung , Chun-chen Yeh
IPC分类号: H01L29/66 , H01L29/32 , H01L29/16 , H01L29/20 , H01L21/311 , H01L21/306 , H01L21/02 , H01L29/78 , H01L29/08
摘要: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.
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公开(公告)号:US20220093627A1
公开(公告)日:2022-03-24
申请号:US17543235
申请日:2021-12-06
发明人: Effendi Leobandung
IPC分类号: H01L27/11556 , H01L27/11524 , H01L29/423 , H01L21/308 , H01L27/11582 , H01L27/1157 , H01L29/51
摘要: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.
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公开(公告)号:US11183419B2
公开(公告)日:2021-11-23
申请号:US16821074
申请日:2020-03-17
发明人: Effendi Leobandung
IPC分类号: H01L21/74 , H01L29/66 , H01L29/06 , H01L23/48 , H01L21/762 , H01L21/768
摘要: Embodiments of the present invention are directed to fabrication methods and resulting semiconductor structures having a bulb-shaped buried interconnect positioned below a shallow trench isolation region. In a non-limiting embodiment of the invention, a cavity is formed below a surface of a substrate. The cavity extends under a portion of a semiconductor fin. The cavity is filled with a sacrificial material and a shallow trench isolation region is formed on the sacrificial material in the cavity. A portion of the shallow trench isolation region is removed to expose a surface of the sacrificial material in the cavity. The sacrificial material is removed from the cavity and replaced with a buried interconnect.
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公开(公告)号:US11176451B2
公开(公告)日:2021-11-16
申请号:US16159205
申请日:2018-10-12
发明人: Yulong Li , Paul M. Solomon , Effendi Leobandung
摘要: Systems and methods for a capacitor based resistive processing unit with symmetrical weight updating include a first capacitor that stores a charge corresponding to a weight value. A readout circuit reads the charge stored in the first capacitor to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. An update circuit updates the weight value stored in the first capacitor, including a second capacitor in communication with the first capacitor to transfer an amount of charge to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.
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