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公开(公告)号：US11990437B2
公开(公告)日：2024-05-21
申请号：US16990499
申请日：2020-08-11
Applicant: International Business Machines Corporation
Inventor： Eric Peter Lewandowski , Jae-Woong Nah , Jeng-Bang Yau , Peter Jerome Sorce
IPC: G06N5/04 , G06F7/38 , G06N10/00 , G06N10/20 , G11C11/44 , H01L23/00 , H10N60/01 , H10N60/80 , H01L21/60
CPC classification number: H01L24/11 , G06F7/381 , G06N10/00 , G06N10/20 , G11C11/44 , H01L24/12 , H01L24/16 , H10N60/0912 , H10N60/805 , H01L2021/60022 , H01L2021/60045 , H01L2021/60067 , H01L2224/11622 , H01L2224/16227
Abstract: In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.
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公开(公告)号：US11916130B2
公开(公告)日：2024-02-27
申请号：US17186533
申请日：2021-02-26
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kuen-Ting Shiu , Tak H. Ning , Jeng-Bang Yau , Cheng-Wei Cheng , Ko-Tao Lee
IPC: H01L29/66 , H01L29/737 , H01L21/308 , H01L29/06 , H01L21/306 , H01L29/205
CPC classification number: H01L29/66318 , H01L21/308 , H01L21/30621 , H01L29/0649 , H01L29/205 , H01L29/737
Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
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公开(公告)号：US11557663B2
公开(公告)日：2023-01-17
申请号：US16661052
申请日：2019-10-23
Applicant: International Business Machines Corporation
Inventor： Karthik Balakrishnan , Bahman Hekmatshoartabari , Alexander Reznicek , Jeng-Bang Yau
IPC: H01L29/66 , H01L29/423 , H01L29/786 , H01L27/108 , H01L29/06 , B82Y10/00 , H01L29/40 , H01L29/739 , H01L29/08
Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
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公开(公告)号：US20210083139A1
公开(公告)日：2021-03-18
申请号：US16572102
申请日：2019-09-16
Applicant: International Business Machines Corporation
Inventor： Alexander Reznicek , Bahman Hekmatshoartabari , Jeng-Bang Yau , Karthik Balakrishnan
IPC: H01L31/119 , H05G1/28 , G01T1/02
Abstract: A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.
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公开(公告)号：US10916651B2
公开(公告)日：2021-02-09
申请号：US16794473
申请日：2020-02-19
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Alexander Reznicek , Tak H. Ning , Jeng-Bang Yau , Bahman Hekmatshoartabari
IPC: H01L29/78 , H01L29/66 , H01L21/28 , H01L21/311 , H01L29/423
Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
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公开(公告)号：US10916629B2
公开(公告)日：2021-02-09
申请号：US16050810
申请日：2018-07-31
Applicant: International Business Machines Corporation
Inventor： Alexander Reznicek , Jeng-Bang Yau , Tak H. Ning , Ghavam G. Shahidi
IPC: H01L29/10 , H01L21/8238 , H01L29/792 , H01L27/11568 , H01L29/66 , H01L27/092 , H01L29/06
Abstract: A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.
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公开(公告)号：US20210028138A1
公开(公告)日：2021-01-28
申请号：US16990499
申请日：2020-08-11
Applicant: International Business Machines Corporation
Inventor： Eric Peter Lewandowski , Jae-Woong Nah , Jeng-Bang Yau , Peter Jerome Sorce
Abstract: In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.
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公开(公告)号：US20200343257A1
公开(公告)日：2020-10-29
申请号：US16391982
申请日：2019-04-23
Applicant: International Business Machines Corporation
Inventor： Jeng-Bang Yau , Alexander Reznicek , Bahman Hekmatshoartabari , Karthik Balakrishnan
IPC: H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L29/786 , G01T1/02
Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.
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公开(公告)号：US20200273967A1
公开(公告)日：2020-08-27
申请号：US16284422
申请日：2019-02-25
Applicant: International Business Machines Corporation
Inventor： Alexander Reznicek , Tak H. Ning , Bahman Hekmatshoartabari , Jeng-Bang Yau
Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.
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10.发明申请
公开(公告)号：US20200066874A1
公开(公告)日：2020-02-27
申请号：US16671844
申请日：2019-11-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Karthik Balakrishnan , Jeng-Bang Yau , Alexander Reznicek , Tak H. Ning
IPC: H01L29/66 , H01L29/423 , H01L29/78 , H01L29/08 , H01L29/06 , H01L27/11521
Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
