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公开(公告)号：US12041856B2
公开(公告)日：2024-07-16
申请号：US17037191
申请日：2020-09-29
摘要： Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.
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公开(公告)号：US11869983B2
公开(公告)日：2024-01-09
申请号：US16817571
申请日：2020-03-12
IPC分类号： H01L29/808 , H01L29/10 , H01L21/02 , H01L29/06 , H01L29/08
CPC分类号： H01L29/8086 , H01L21/02576 , H01L21/02579 , H01L29/0661 , H01L29/0665 , H01L29/0847 , H01L29/1045 , H01L29/1066
摘要： A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels. In some embodiments, the junction gates are formed all-around the channel surfaces. As a result, the current flowing in the channels between the source and drain can be controlled with less voltage applied to the gates and less power consumption.
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公开(公告)号：US11557663B2
公开(公告)日：2023-01-17
申请号：US16661052
申请日：2019-10-23
IPC分类号： H01L29/66 , H01L29/423 , H01L29/786 , H01L27/108 , H01L29/06 , B82Y10/00 , H01L29/40 , H01L29/739 , H01L29/08
摘要： A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
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公开(公告)号：US11424361B2
公开(公告)日：2022-08-23
申请号：US17227302
申请日：2021-04-10
IPC分类号： H01L29/78 , H01L27/092 , H01L29/10 , H01L21/8238 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/786
摘要： A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).
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公开(公告)号：US11189701B1
公开(公告)日：2021-11-30
申请号：US17118819
申请日：2020-12-11
IPC分类号： H01L29/417 , H01L29/737 , H01L29/66 , H01L29/10 , H01L29/73
摘要： Vertical bipolar junction transistors (VBJTs), each with one or more resistors connected in a circuit in different circuit configurations, are disclosed. The VBJT has an emitter substructure that includes an emitter layer, a collector, an intrinsic base, one or more doped epitaxy regions, and one or more resistors. The intrinsic base, the doped epitaxy region(s), and the resistor(s) are stacked upon one another in a channel between the emitter layer and the collector. Various circuit configurations and structures are described including a common-collector circuit, a common-emitter circuit, and an emitter-degenerate circuit. Methods of making these configuration/structures are disclosed.
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公开(公告)号：US20210288187A1
公开(公告)日：2021-09-16
申请号：US16817571
申请日：2020-03-12
IPC分类号： H01L29/808 , H01L29/10 , H01L29/08 , H01L29/06 , H01L21/02
摘要： A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels. In some embodiments, the junction gates are formed all-around the channel surfaces. As a result, the current flowing in the channels between the source and drain can be controlled with less voltage applied to the gates and less power consumption.
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公开(公告)号：US11094819B2
公开(公告)日：2021-08-17
申请号：US16705662
申请日：2019-12-06
IPC分类号： H01L29/78 , H01L27/092 , H01L29/10 , H01L21/8238 , H01L29/417 , H01L29/66 , H01L29/08
摘要： A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).
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公开(公告)号：US10991823B2
公开(公告)日：2021-04-27
申请号：US15783781
申请日：2017-10-13
IPC分类号： H01L21/8234 , H01L29/78 , H01L29/10 , H01L29/165 , H01L27/088 , H01L29/66 , H01L21/02 , H01L21/762 , H01L29/161 , H01L27/082
摘要： A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
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公开(公告)号：US10964709B2
公开(公告)日：2021-03-30
申请号：US16352222
申请日：2019-03-13
IPC分类号： H01L27/11521 , H01L27/11568 , H01L27/112 , H01L27/092 , H01L29/78 , H01L27/06 , H01L27/12 , G11C16/04 , H01L27/11551 , H01L29/788
摘要： A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.
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公开(公告)号：US20210083139A1
公开(公告)日：2021-03-18
申请号：US16572102
申请日：2019-09-16
IPC分类号： H01L31/119 , H05G1/28 , G01T1/02
摘要： A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.
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