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公开(公告)号：US20170220318A1
公开(公告)日：2017-08-03
申请号：US15011735
申请日：2016-02-01
CPC分类号： G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/5443 , G06F2207/483
摘要： A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.
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公开(公告)号：US20190317726A1
公开(公告)日：2019-10-17
申请号：US16453695
申请日：2019-06-26
摘要： A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
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公开(公告)号：US10416962B2
公开(公告)日：2019-09-17
申请号：US14873469
申请日：2015-10-02
发明人： Steven R. Carlough , Juergen Haess , Michael Klein , Klaus M. Kroener , Petra Leber , Silvia M. Mueller , Kerstin Schelm
摘要： Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.
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公开(公告)号：US09767073B2
公开(公告)日：2017-09-19
申请号：US14733129
申请日：2015-06-08
CPC分类号： G06F17/10 , G06F7/535 , G06F7/5375
摘要： An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.
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公开(公告)号：US09658828B2
公开(公告)日：2017-05-23
申请号：US14873450
申请日：2015-10-02
CPC分类号： G06F7/485 , G06F7/49915 , G06F7/49947
摘要： Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.
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公开(公告)号：US10649730B2
公开(公告)日：2020-05-12
申请号：US16453695
申请日：2019-06-26
摘要： A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
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公开(公告)号：US10459689B2
公开(公告)日：2019-10-29
申请号：US14735271
申请日：2015-06-10
摘要： Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.
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公开(公告)号：US20190235841A1
公开(公告)日：2019-08-01
申请号：US16380267
申请日：2019-04-10
摘要： A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.
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公开(公告)号：US20180203672A1
公开(公告)日：2018-07-19
申请号：US15409778
申请日：2017-01-19
摘要： A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.
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公开(公告)号：US20170068517A1
公开(公告)日：2017-03-09
申请号：US15354151
申请日：2016-11-17
CPC分类号： G06F7/485 , G06F7/49915 , G06F7/49947
摘要： Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.
摘要翻译： 提供算术逻辑电路用于对第一和第二浮点数进行浮点运算加减运算。 该方法包括：通过压缩函数变换第一和第二数字来产生第一或第二数字的保护数字; 根据算术运算确定结果，转换浮点数的总和以及经变换的浮点数的第一和第二差，并且通过向结果另外添加一个值来确定相应的结果加1; 产生用于舍入最终结果的注入值; 基于变换的第一和第二数字和注入值产生喷射进位值; 并根据注入进位值和结束周围进位信号从结果中选择最终结果，结果加1和最低有效数字。
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