公开(公告)号：US10998420B2

公开(公告)日：2021-05-04

申请号：US15945305

申请日：2018-04-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kuen-Ting Shiu ,  Tak H. Ning ,  Jeng-Bang Yau ,  Cheng-Wei Cheng ,  Ko-Tao Lee

IPC: H01L29/66 ,  H01L29/737 ,  H01L21/308 ,  H01L29/06 ,  H01L21/306 ,  H01L29/205

Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

公开(公告)号：US20190140424A1

公开(公告)日：2019-05-09

申请号：US16239657

申请日：2019-01-04

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Effendi Leobandung ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01S5/183 ,  H01L31/18 ,  H01S5/02 ,  H01L31/0232 ,  H01L31/0304 ,  H01L33/30 ,  H01L33/12 ,  H01L33/10 ,  H01L33/00 ,  H01L31/105 ,  H01S5/187 ,  H01S5/343 ,  H01L33/02

CPC classification number: H01S5/18377 ,  H01L31/02327 ,  H01L31/0304 ,  H01L31/105 ,  H01L31/1852 ,  H01L33/0012 ,  H01L33/0066 ,  H01L33/025 ,  H01L33/105 ,  H01L33/12 ,  H01L33/30 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/0262 ,  H01S5/18361 ,  H01S5/187 ,  H01S5/3432 ,  H01S5/34366

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8

公开(公告)号：US09865769B2

公开(公告)日：2018-01-09

申请号：US14665115

申请日：2015-03-23

Applicant: International Business Machines Corporation

Inventor： Can Bayram ,  Stephen W. Bedell ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L21/46 ,  H01L21/00 ,  H01L21/469 ,  H01L33/00 ,  H01L33/02 ,  H01L33/60 ,  H01L33/12 ,  H01L33/62 ,  H01L31/18

CPC classification number: H01L33/025 ,  H01L31/1836 ,  H01L31/1852 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/60 ,  H01L33/62 ,  H01L2924/3512

Abstract: A method of forming, and corresponding structure, of an LED device where an LED and the contacts for the device are formed on a surface of the substrate, and the substrate is spalled just below the surface of the substrate.

公开(公告)号：US09660116B2

公开(公告)日：2017-05-23

申请号：US15093255

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith E. Fogel ,  Jeehwan Kim ,  Jae-Woong Nah ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L31/0352 ,  H01L31/0236 ,  H01L31/18 ,  H01L31/0224

CPC classification number: H01L31/035227 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/0352 ,  H01L31/1804 ,  Y02E10/50

Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.

公开(公告)号：US09608160B1

公开(公告)日：2017-03-28

申请号：US15016799

申请日：2016-02-05

Applicant: International Business Machines Corporation

Inventor： Can Bayram ,  Cheng-Wei Cheng ,  Tayfun Gokmen ,  Ning Li ,  John A. Ott ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L29/15 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01L33/22 ,  H01L33/18 ,  H01L33/36

CPC classification number: H01L33/007 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L33/12 ,  H01L33/16 ,  H01L33/18 ,  H01L33/22 ,  H01L33/32 ,  H01L33/36 ,  H01L2933/0016 ,  H01S5/021 ,  H01S5/3201 ,  H01S5/3202 ,  H01S5/34333

Abstract: After forming patterned dielectric material structures over a (100) silicon substrate, portions of the silicon substrate that are not covered by the patterned dielectric material structures are removed to provide a plurality of openings within the silicon substrate. Each opening exposes a surface of the silicon substrate having a (111) crystalline plane. A buffer layer is then formed on the exposed surfaces of the patterned dielectric material structures and the silicon substrate. A dual phase Group III nitride structure including a cubic phase region is formed filling a space between each neighboring pair of the patterned dielectric material structures and one of the openings located beneath the space. Finally, at least one Group III nitride layer is epitaxially deposited over the cubic phase region of the dual phase Group III nitride structure.

公开(公告)号：US20170075062A1

公开(公告)日：2017-03-16

申请号：US15363471

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: G02B6/12 ,  H01S5/30 ,  H01S5/343 ,  H01S5/026 ,  H01L33/00 ,  H01L31/173 ,  H01L31/18 ,  H01L31/0232 ,  H01L33/50 ,  G02B6/13 ,  G02B6/122

CPC classification number: G02B6/12004 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/131 ,  G02B6/132 ,  G02B6/136 ,  G02B2006/12121 ,  G02B2006/12123 ,  H01L27/1203 ,  H01L31/0232 ,  H01L31/02322 ,  H01L31/173 ,  H01L31/1836 ,  H01L33/007 ,  H01L33/502 ,  H01S5/0261 ,  H01S5/0262 ,  H01S5/3013 ,  H01S5/343 ,  H02S40/44 ,  H04B10/801

Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.

Abstract translation: 一种电气装置，其包括位于基板的第一部分上的第一半导体器件和位于所述基板的第三部分上的第二半导体器件，其中所述基板的第一和第三部分被所述基板的第二部分分开。 层间电介质层存在于衬底的第一，第二和第三部分上。 层间电介质层存在于第一和第二半导体器件上。 光学互连件位于半导体衬底的第二部分上方。 光学互连件的至少一个材料层包括外延材料，该外延材料通过延伸穿过至少一个层间电介质层的通孔与衬底的第二部分内的种子表面直接接触。

公开(公告)号：US09595805B2

公开(公告)日：2017-03-14

申请号：US14493022

申请日：2014-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L21/02 ,  H01L29/06 ,  H01L23/495 ,  H01S5/02 ,  G02B6/42 ,  H01S5/026 ,  H01S5/042

CPC classification number: H01S5/021 ,  G02B6/12004 ,  G02B6/1228 ,  G02B6/131 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/12061 ,  G02B2006/12078 ,  G02B2006/12121 ,  G02B2006/12176 ,  H01S5/026 ,  H01S5/0425 ,  H01S5/343 ,  H01S2301/176

Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.

Abstract translation: 一种半导体器件，包括：衬底结构，其包括半导体材料层，所述半导体材料层直接存在于所述衬底结构的第一部分中的埋置电介质层上;以及隔离电介质材料，其直接存在于所述衬底的第二部分中的所述掩埋电介质层上 结构体。 半导体器件还包括III-V光电子器件，其在衬底结构的第二部分的第一区域中与隔离电介质材料直接接触。 电介质波导在衬底结构的第二部分的第二区域中与隔离电介质材料直接接触。

公开(公告)号：US09590393B2

公开(公告)日：2017-03-07

申请号：US15095599

申请日：2016-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L31/0232 ,  H01S5/30 ,  H01L31/173 ,  H04B10/80 ,  G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136 ,  H01L27/12 ,  H01S5/026 ,  H01S5/343

CPC classification number: G02B6/12004 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/131 ,  G02B6/132 ,  G02B6/136 ,  G02B2006/12121 ,  G02B2006/12123 ,  H01L27/1203 ,  H01L31/0232 ,  H01L31/02322 ,  H01L31/173 ,  H01L31/1836 ,  H01L33/007 ,  H01L33/502 ,  H01S5/0261 ,  H01S5/0262 ,  H01S5/3013 ,  H01S5/343 ,  H02S40/44 ,  H04B10/801

Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.

Abstract translation: 一种电气装置，其包括位于基板的第一部分上的第一半导体器件和位于所述基板的第三部分上的第二半导体器件，其中所述基板的第一和第三部分被所述基板的第二部分分开。 层间电介质层存在于衬底的第一，第二和第三部分上。 层间电介质层存在于第一和第二半导体器件上。 光学互连件位于半导体衬底的第二部分上方。 光学互连件的至少一个材料层包括外延材料，该外延材料通过延伸穿过至少一个层间电介质层的通孔与衬底的第二部分内的种子表面直接接触。

公开(公告)号：US20170062232A1

公开(公告)日：2017-03-02

申请号：US14839755

申请日：2015-08-28

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Leathen Shi ,  Kuen-Ting Shiu

IPC: H01L21/306 ,  H01L29/201 ,  H01L21/02

CPC classification number: H01L21/30617 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/0273 ,  H01L21/30612 ,  H01L21/67086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/7813 ,  H01L29/20 ,  H01L29/201 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.

Abstract translation: 提出了一种执行外延剥离的方法，允许重新使用III-V衬底来生长III-V器件。 接收的样品包括具有顶表面的生长衬底，在顶表面上的牺牲层以及牺牲层上的器件层。 该衬底被支撑在容器内部，并且容器中充满湿蚀刻剂，使得湿蚀刻剂逐渐地蚀刻掉牺牲层并且器件层远离生长衬底。 在用湿蚀刻剂填充容器的同时，将样品支撑在容器中，使得生长衬底的顶表面与湿蚀刻剂的最上表面不平行。 以这种方式进行，剥离过程需要几乎没有样品的单独设置，并且能够进行批处理和高产量。

公开(公告)号：US09395489B2

公开(公告)日：2016-07-19

申请号：US14509506

申请日：2014-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L29/06 ,  H01L29/12 ,  G02B6/12 ,  H01S5/343 ,  H01S5/02 ,  H01L31/0296 ,  H01L31/18 ,  G02B6/122

CPC classification number: G02B6/12004 ,  G02B6/1228 ,  H01L27/108 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/1443 ,  H01L29/73 ,  H01L29/772 ,  H01L29/78 ,  H01L29/785 ,  H01L29/808 ,  H01L29/872 ,  H01L31/02325 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/105 ,  H01L31/16 ,  H01L31/1852 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/343

Abstract: An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type IV semiconductor substrate, and an optoelectronic light emission device of type III-V semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate. A dielectric waveguide is present on a second portion of the type IV semiconductor substrate. An optoelectronic light detection device of type III-V semiconductor material is present on a third portion of the type IV semiconductor device. The dielectric waveguide is positioned between and aligned with the optoelectronic tight detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device.

Abstract translation: 在一个实施例中的电气装置包括位于IV型半导体衬底的第一部分上的第一半导体器件和与第一半导体器件电连通的III-V族半导体材料的光电发光器件。 光电子发射器件位于IV型半导体衬底的第一部分上与第一半导体器件相邻的位置。 电介质波导存在于IV型半导体衬底的第二部分上。 III型半导体材料的光电子检测器件存在于IV型半导体器件的第三部分上。 电介质波导位于光电紧密检测装置和光电子发射装置之间并与其对准，以将光信号从光电子发射装置传输到光电子光检测装置。