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    Stacked nanosheet transistor with defect free channel
    1.
    发明授权
    Stacked nanosheet transistor with defect free channel 有权

    公开(公告)号：US12176416B2

    公开(公告)日：2024-12-24

    申请号：US18324240

    申请日：2023-05-26

    Applicant: International Business Machines Corporation

    Inventor： Lan Yu ,  Kangguo Cheng ,  Heng Wu ,  Chen Zhang

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

    Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

    CONTACT FORMATION FOR VERTICAL FIELD EFFECT TRANSISTORS
    6.
    发明申请
    CONTACT FORMATION FOR VERTICAL FIELD EFFECT TRANSISTORS 有权

    公开(公告)号：US20230082449A1

    公开(公告)日：2023-03-16

    申请号：US17447904

    申请日：2021-09-16

    Applicant: International Business Machines Corporation

    Inventor： Heng Wu ,  Lan Yu ,  Samuel Sung Shik Choi ,  Ruilong Xie

    IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66

    Abstract: A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

    Nanosheet transistors with inner airgaps
    7.
    发明授权
    Nanosheet transistors with inner airgaps 有权

    公开(公告)号：US11557651B2

    公开(公告)日：2023-01-17

    申请号：US17132798

    申请日：2020-12-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Heng Wu ,  Ruilong Xie ,  Alexander Reznicek ,  Lan Yu

    IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

    Abstract: A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.

    Stacked vertical field effect transistor with self-aligned junctions
    10.
    发明授权
    Stacked vertical field effect transistor with self-aligned junctions 有权

    公开(公告)号：US11177369B2

    公开(公告)日：2021-11-16

    申请号：US16582790

    申请日：2019-09-25

    Applicant: International Business Machines Corporation

    Inventor： Lan Yu ,  Xin Miao ,  Chen Zhang ,  Heng Wu ,  Kangguo Cheng

    IPC: H01L27/11 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

    Abstract: A method of forming a semiconductor device and resulting structure in which a trench is formed extending through a plurality of layers on a semiconductor substrate. The plurality of layers includes a sequence of dielectric materials. A first portion of the plurality of layers corresponds to a bottom vertical field effect transistor (VFET) and a second portion of the plurality of layers corresponds to a top VFET. A sacrificial layer separates the bottom VFET from the top VFET. A fin is formed within the trench by epitaxially growing a semiconductor material. A hard mask is formed above a central portion of the plurality of layers. Portions of the plurality of layers not covered by the hard mask are removed. The first portion of the plurality of layers is covered to remove the sacrificial layer. The recess resulting from the removal of the sacrificial layer is filled with an oxide material.

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