公开(公告)号：US10050171B2

公开(公告)日：2018-08-14

申请号：US15408012

申请日：2017-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/028 ,  H01L31/103 ,  G02B6/12

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

公开(公告)号：US20180090432A1

公开(公告)日：2018-03-29

申请号：US15824906

申请日：2017-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L23/528 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768 ,  H01L21/683 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L23/528 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/0649 ,  H01L2221/68327 ,  H01L2221/68372

Abstract: A back-side device structure with a silicon-on-insulator substrate that includes: a first dielectric layer that includes a first via that communicates with a trench, a contact plug that fills the trench, and a first contact formed in a second dielectric layer. The first contact fills the first via and connects with the contact plug and a wire formed in a third dielectric layer. A final substrate is connected to a buried insulator layer of the silicon-on-insulator substrate such that the contact plug contacts metallization of the final substrate.

公开(公告)号：US20180068891A1

公开(公告)日：2018-03-08

申请号：US15799862

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/74 ,  H01L21/762 ,  H01L29/10 ,  H01L29/06 ,  H01L27/12 ,  H01L21/683 ,  H01L23/482

CPC classification number: H01L21/76895 ,  H01L21/6835 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/4825 ,  H01L23/4827 ,  H01L23/53271 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1087 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. An electrically-conducting connection is formed in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

公开(公告)号：US20180068887A1

公开(公告)日：2018-03-08

申请号：US15812320

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US09852944B2

公开(公告)日：2017-12-26

申请号：US15274406

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/30 ,  H01L21/768 ,  H01L23/482 ,  H01L21/762 ,  H01L23/532 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L21/683 ,  H01L21/74

CPC classification number: H01L21/76895 ,  H01L21/6835 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/4825 ,  H01L23/4827 ,  H01L23/53271 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1087 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

公开(公告)号：US20160372416A1

公开(公告)日：2016-12-22

申请号：US15234913

申请日：2016-08-11

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L23/528 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/0649 ,  H01L2221/68327 ,  H01L2221/68372

Abstract: A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the device layer and that partially extends through the buried insulator layer, at least one dielectric layer that is formed on the device layer and includes a first opening that communicates with the trench and a contact plug that fills the trench. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. The contact plug is externally connected with a source to provide signals to the back-side device structure through a wire formed in the at least one dielectric layer.

Abstract translation: 一种具有绝缘体上硅衬底的背面器件结构，其包括器件层，掩埋绝缘体层，延伸穿过器件层并且部分延伸穿过掩埋绝缘体层的沟槽，至少一个电介质层是 形成在器件层上并且包括与沟槽连通的第一开口和填充沟槽的接触塞。 最终的衬底连接到埋入的绝缘体层，使得接触插塞接触最终衬底的金属化。 接触插头与源外部连接，以通过形成在至少一个电介质层中的导线向后侧器件结构提供信号。

公开(公告)号：US09514987B1

公开(公告)日：2016-12-06

申请号：US14744681

申请日：2015-06-19

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/482

CPC classification number: H01L21/76895 ,  H01L21/6835 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/4825 ,  H01L23/4827 ,  H01L23/53271 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1087 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: Device structures and fabrication methods for a backside contact to a final substrate An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

Abstract translation: 用于与最终衬底的背面接触的器件结构和制造方法形成延伸穿过绝缘体上硅衬底的器件层并且部分地穿过绝缘体上硅衬底的掩埋绝缘体层的导电连接。 在形成导电连接之后，去除绝缘体上硅衬底的处理晶片。 在移除手柄晶片之后，部分去除掩埋绝缘体层以露出导电连接。 在埋入绝缘体层被部分去除之后，最后的衬底被耦合到埋入绝缘体层，使得导电连接与最终衬底耦合。

公开(公告)号：US09002156B2

公开(公告)日：2015-04-07

申请号：US13872396

申请日：2013-04-29

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/4214

Abstract: An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.

Abstract translation: 光波导结构可以包括位于半导体结构内的光波导结构和光耦合器。 光耦合器可以包括位于半导体结构的电互连区域内的金属结构，由此金属结构从电互连区域的顶表面以基本弯曲的形状向下延伸并且耦合到光波导结构。 光耦合器还可以包括限定在金属结构内的光信号引导区域，由此光耦合器从顶表面接收光信号并将光信号耦合到光波导结构，使得光信号传播在 顶表面并且在光波导结构处基本上水平。

公开(公告)号：US08951896B2

公开(公告)日：2015-02-10

申请号：US13929955

申请日：2013-06-28

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Jeffrey E. Hanrahan ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Dale W. Martin ,  Gerd Pfeiffer ,  James A. Slinkman

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/04

CPC classification number: H01L21/76251 ,  H01L21/04 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324

Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.

公开(公告)号：US20150001622A1

公开(公告)日：2015-01-01

申请号：US13929256

申请日：2013-06-27

Applicant: International Business Machines Corporation

Inventor： Michel J. Abou-Khalil ,  Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  James A. Slinkman

IPC: H01L29/786 ,  H01L21/28

CPC classification number: H01L29/78654 ,  H01L21/28123 ,  H01L21/84 ,  H01L29/66613

Abstract: An integrated recessed thin body field effect transistor (FET) and methods of manufacture are disclosed. The method includes recessing a portion of a semiconductor material. The method further includes forming at least one gate structure within the recessed portion of the semiconductor material.

Abstract translation: 公开了集成的凹陷薄体场效应晶体管（FET）及其制造方法。 该方法包括使半导体材料的一部分凹陷。 该方法还包括在半导体材料的凹陷部分内形成至少一个栅极结构。