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    SILICON ON SAPPHIRE SUBSTRATE FOR EDGE COMPUTER
    4.
    发明申请
    SILICON ON SAPPHIRE SUBSTRATE FOR EDGE COMPUTER 有权

    公开(公告)号：US20230080397A1

    公开(公告)日：2023-03-16

    申请号：US17477520

    申请日：2021-09-16

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Devendra K. Sadana ,  Ning Li

    IPC分类号： H01L25/16 ,  H01L23/66

    摘要： A computing device is provided. The computing device includes a sapphire substrate having a first surface and a second surface opposed to the first surface, a light receiving device having a first surface and a second surface opposed to the first surface, the second surface of the light receiving device coupled to the first surface of the sapphire substrate, a memory coupled to the first surface of the light receiving device, and an antenna coupled to the first surface of the sapphire substrate.

    Superconductor-semiconductor Josephson junction
    5.
    发明授权
    Superconductor-semiconductor Josephson junction 有权

    公开(公告)号：US11581472B2

    公开(公告)日：2023-02-14

    申请号：US16534882

    申请日：2019-08-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Devendra K. Sadana ,  Ning Li ,  Stephen W. Bedell ,  Sean Hart ,  Patryk Gumann

    IPC分类号： H01L39/02 ,  G06N10/00 ,  H01L39/22

    摘要： A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

    Phase change device with interfacing first and second semiconductor layers
    7.
    发明授权
    Phase change device with interfacing first and second semiconductor layers 有权

    公开(公告)号：US11355703B2

    公开(公告)日：2022-06-07

    申请号：US16903245

    申请日：2020-06-16

    申请人： International Business Machines Corporation

    发明人： Ning Li ,  Devendra K. Sadana

    IPC分类号： H01L45/00 ,  G11C13/00

    摘要： According to some embodiments of the present invention a phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface. The second semiconductor material can transition between a second amorphous state and a second crystalline state at one or more second conditions. A first electrode in physical and electrical contact with the first electrode surface of the first semiconductor layer and a second electrode in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first conditions and second conditions are different. Therefore, in some embodiments, the first and second semiconductor materials can be in different amorphous and/or crystalline states. The layers can have split amorphous/crystalline states. By controlling how the layers are split, the PCD can be in different resistive states.