公开(公告)号：US10784346B2

公开(公告)日：2020-09-22

申请号：US16516815

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/10 ,  H01L21/225 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/732

Abstract: A method includes forming a base layer on a top surface of a substrate. A dielectric layer is formed on exposed surfaces of the base layer. A hardmask layer is formed on the base layer and the dielectric layer. A pattern is formed from the hardmask with a first opening and a second opening. Portions of a dielectric layer are removed from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer. Deposits of a dopant-containing layer are limited on the exposed surfaces of: a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window.

公开(公告)号：US10770557B2

公开(公告)日：2020-09-08

申请号：US15982370

申请日：2018-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L29/49 ,  H01L29/47 ,  H01L27/12 ,  H01L29/51

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US10692753B2

公开(公告)日：2020-06-23

申请号：US16240304

申请日：2019-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/764 ,  H01L21/306 ,  H01L29/786 ,  H01L27/12 ,  H01L21/027 ,  H01L21/266

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US10431654B2

公开(公告)日：2019-10-01

申请号：US14749836

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/10 ,  H01L21/225 ,  H01L21/324 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/732

Abstract: Device structure and fabrication methods for a bipolar junction transistor. A base layer is formed and an emitter is formed on a first portion of the base layer. A dopant-containing layer is deposited on a second portion of the base layer. Dopant is transferred from the dopant-containing layer into the second portion of the base layer to define an extrinsic base of the device structure.

公开(公告)号：US10109716B2

公开(公告)日：2018-10-23

申请号：US14864020

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/47

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US09759868B2

公开(公告)日：2017-09-12

申请号：US14933705

申请日：2015-11-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brett Cucci ,  Paul F. Fortier ,  Jeffrey P. Gambino ,  Robert K. Leidy ,  Qizhi Liu ,  Richard J. Rassel

IPC: G02B6/30 ,  G02B6/13

CPC classification number: G02B6/30 ,  G02B6/4243 ,  G02B6/428

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures for preventing dicing damage on photonics wafers. The structure includes: an optical waveguide structure to optical fiber interface formed on an integrated circuit; and a groove formed in a substrate and which includes a structure preventing a fluid pressure of a dicing operation from damaging the substrate along the groove.

公开(公告)号：US09735259B2

公开(公告)日：2017-08-15

申请号：US14834699

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L29/73 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L27/082 ,  H01L27/06 ,  H01L29/417 ,  H01L21/8249

CPC classification number: H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

Abstract: Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

公开(公告)号：US09633894B2

公开(公告)日：2017-04-25

申请号：US14963530

申请日：2015-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/266 ,  H01L21/764 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US09437539B2

公开(公告)日：2016-09-06

申请号：US14830816

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/762 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US20160197167A1

公开(公告)日：2016-07-07

申请号：US15073763

申请日：2016-03-18

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L29/732 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Abstract translation: 各种具体实施例包括具有堆叠区域的集成电路（IC）结构; 以及位于所述堆叠区域下方并接触的硅衬底，所述硅衬底包括：包含掺杂子集电极区域的硅区域; 一组覆盖硅区的隔离区; 所述基极区域在所述隔离区域之间并且在所述堆叠区域之下，所述基极区域包括与所述堆叠区域接触的本征基极，与所述本征基极和所述堆叠区域接触的非本征基极，以及接触所述外部基极的非晶化非本征基极接触区域 ; 在所述一组隔离区域之间的集电极区域; 在所述一组隔离区域和所述基底区域之下的底切集电极 - 基极区域; 以及通过掺杂子集电极区域与本征基极之下的集电极区域和集电极 - 基极区域接触的集电极接触区域。