Extrinsic base doping for bipolar junction transistors

    公开(公告)号:US10784346B2

    公开(公告)日:2020-09-22

    申请号:US16516815

    申请日:2019-07-19

    Abstract: A method includes forming a base layer on a top surface of a substrate. A dielectric layer is formed on exposed surfaces of the base layer. A hardmask layer is formed on the base layer and the dielectric layer. A pattern is formed from the hardmask with a first opening and a second opening. Portions of a dielectric layer are removed from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer. Deposits of a dopant-containing layer are limited on the exposed surfaces of: a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window.

    Tunable breakdown voltage RF FET devices

    公开(公告)号:US10770557B2

    公开(公告)日:2020-09-08

    申请号:US15982370

    申请日:2018-05-17

    Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

    Turnable breakdown voltage RF FET devices

    公开(公告)号:US10109716B2

    公开(公告)日:2018-10-23

    申请号:US14864020

    申请日:2015-09-24

    Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

    Vertical P-Type, N-Type, P-Type (PNP) Junction Integrated Circuit (IC) Structure
    10.
    发明申请
    Vertical P-Type, N-Type, P-Type (PNP) Junction Integrated Circuit (IC) Structure 有权
    垂直P型,N型,P型(PNP)结集成电路(IC)结构

    公开(公告)号:US20160197167A1

    公开(公告)日:2016-07-07

    申请号:US15073763

    申请日:2016-03-18

    Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

    Abstract translation: 各种具体实施例包括具有堆叠区域的集成电路(IC)结构; 以及位于所述堆叠区域下方并接触的硅衬底,所述硅衬底包括:包含掺杂子集电极区域的硅区域; 一组覆盖硅区的隔离区; 所述基极区域在所述隔离区域之间并且在所述堆叠区域之下,所述基极区域包括与所述堆叠区域接触的本征基极,与所述本征基极和所述堆叠区域接触的非本征基极,以及接触所述外部基极的非晶化非本征基极接触区域 ; 在所述一组隔离区域之间的集电极区域; 在所述一组隔离区域和所述基底区域之下的底切集电极 - 基极区域; 以及通过掺杂子集电极区域与本征基极之下的集电极区域和集电极 - 基极区域接触的集电极接触区域。

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