公开(公告)号：US20250048675A1

公开(公告)日：2025-02-06

申请号：US18365990

申请日：2023-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  James P. Mazza ,  Nicholas Anthony Lanzillo ,  David Wolpert

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.

公开(公告)号：US20250022795A1

公开(公告)日：2025-01-16

申请号：US18349999

申请日：2023-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Reinaldo Vega ,  Albert M. Chu ,  Brent A. Anderson

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a device layer having a frontside and a backside and including a transistor that includes a source/drain region at the backside of the device layer; a first and a second backside metal line with the source/drain region at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and a backside local interconnect that conductively connects the source/drain region of the transistor with the second backside metal line, where the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line. Methods for forming the same are also provided.

公开(公告)号：US20240339523A1

公开(公告)日：2024-10-10

申请号：US18063987

申请日：2022-12-09

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Julien Frougier ,  Reinaldo Vega

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7827 ,  H01L29/7851

Abstract: One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device, and more particularly for fabricating at least a portion of a vertical transport field effect transistor. The semiconductor device comprises a field-effect transmitter comprising a substrate, a fin extending outwardly from the substrate, a source/drain region having a first portion disposed between the substrate and the fin and stacked with the fin and the substrate along a common extension direction of the fin, and an excess section of semiconductor material disposed adjacent the first portion of the source/drain region and positioned other than stacked together with the substrate and the fin, wherein the semiconductor material of the excess section is different from a material of the fin and different from a material of the source/drain region.

公开(公告)号：US20240145578A1

公开(公告)日：2024-05-02

申请号：US18050560

申请日：2022-10-28

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Ruilong Xie ,  Shogo Mochizuki ,  Julien Frougier ,  Ravikumar Ramachandran

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of the invention include a transistor comprising a gate region and a source/drain region. A first isolation layer is under the gate region. A second isolation layer is separated from the first isolation layer by a third isolation layer.

公开(公告)号：US20240096786A1

公开(公告)日：2024-03-21

申请号：US17934195

申请日：2022-09-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Albert M. Chu ,  Reinaldo Vega ,  Ruilong Xie

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/5283

Abstract: An interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.

公开(公告)号：US11916099B2

公开(公告)日：2024-02-27

申请号：US17341489

申请日：2021-06-08

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  David Wolpert ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/51 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L29/516

Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

公开(公告)号：US11707002B2

公开(公告)日：2023-07-18

申请号：US17233968

申请日：2021-04-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jianshi Tang ,  Takashi Ando ,  Reinaldo Vega ,  Praneet Adusumilli

IPC: H01L45/00 ,  H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10B63/80 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8416

Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

公开(公告)号：US20230178621A1

公开(公告)日：2023-06-08

申请号：US17544328

申请日：2021-12-07

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Yao Yao ,  Andrew M. Greene ,  Veeraraghavan S. Basker ,  Pietro Montanini ,  Jingyun Zhang ,  Robert Robison

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823418

Abstract: A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

公开(公告)号：US20220173312A1

公开(公告)日：2022-06-02

申请号：US17106286

申请日：2020-11-30

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Anirban Chandra ,  Takashi Ando ,  Cheng Chi ,  Reinaldo Vega

IPC: H01L45/00

Abstract: A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.

公开(公告)号：US20210408233A1

公开(公告)日：2021-12-30

申请号：US16916736

申请日：2020-06-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Kangguo Cheng ,  Chanro Park ,  Juntao Li

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.