公开(公告)号：US12107168B2

公开(公告)日：2024-10-01

申请号：US17411618

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Junli Wang ,  Dechao Guo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7855 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1033

Abstract: A stacked FET structure having independently tuned gate lengths is provided to maximize the benefit of each FET within the stacked FET structure. Notably, a vertically stacked FET structure is provided in which a bottom FET has a different gate length than a top FET. In some embodiments, a dielectric spacer can be present laterally adjacent to the bottom FET and the top FET. In such an embodiment, the dielectric spacer can have a first portion that is located laterally adjacent to the bottom FET that has a different thickness than a second portion of the dielectric spacer that is located laterally adjacent the top FET.

公开(公告)号：US12034005B2

公开(公告)日：2024-07-09

申请号：US17133157

申请日：2020-12-23

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Ruqiang Bao ,  Dechao Guo ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845

Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).

公开(公告)号：US20240194670A1

公开(公告)日：2024-06-13

申请号：US18078245

申请日：2022-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Fee Li Lie ,  Michael P. Belyansky ,  Matt Malley

IPC: H01L27/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32145 ,  H01L2224/83896

Abstract: A multi-layer stacked semiconductor device includes a first integrated circuit device and a bonding insulator layer formed upon the first integrated circuit device. The bonding insulator layer includes an insulating material layer and an etch stop layer. The semiconductor device also includes a second integrated circuit device formed over the first integrated circuit device in a stacked configuration. The semiconductor device also includes a bonding insulator layer formed between the second integrated circuit device and the insulating material layer. The insulating material layer and the bonding insulator layer are bonded adjacent to one another.

公开(公告)号：US20240178072A1

公开(公告)日：2024-05-30

申请号：US18070050

申请日：2022-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Eric Miller ,  Dechao Guo

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Semiconductor devices and methods of forming the same include a first transistor in a first region having a first work function metal layer. A second transistor in a second region has a second work function metal layer that overlaps a portion of the first work function metal layer and that has a vertical part above the portion of the first work function metal layer.

公开(公告)号：US20240105769A1

公开(公告)日：2024-03-28

申请号：US17935992

申请日：2022-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shahab Siddiqui ,  Ruqiang Bao ,  Charlotte DeWan Adams ,  Curtis S. Durfee ,  Anthony I. Chou ,  Barry Paul Linder ,  Ravikumar Ramachandran ,  Dechao Guo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.

公开(公告)号：US20230261074A1

公开(公告)日：2023-08-17

申请号：US17650671

申请日：2022-02-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Jingyun Zhang ,  Jing Guo

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device including a first nanosheet device located on a substrate. The first nanosheet device includes a first plurality of nanosheets and each of the first plurality of nanosheets are surround by a first dipole. The first dipole has a first concentration of a first dipole material. A second nanosheet device located on the substrate. The second nanosheet device includes a second plurality of nanosheets and each of the second plurality of nanosheets are surround by a second dipole. The second dipole has a second concentration of a second dipole material. The first concentration and the second concentration are different.

公开(公告)号：US20230197721A1

公开(公告)日：2023-06-22

申请号：US17553967

申请日：2021-12-17

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael P. Belyansky ,  Dechao Guo ,  Junli Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/04 ,  H01L23/00

CPC classification number: H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/785 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/045 ,  H01L24/83 ,  H01L2224/83896

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures that leverage wafer bonding techniques to provide stacked field effect transistors (SFETs) with high-quality N/P junction isolation. In a non-limiting embodiment of the invention, a first semiconductor structure is formed on a first wafer and a second semiconductor structure is formed on a second wafer. The first wafer is positioned with respect to the second wafer such that a top surface of the first semiconductor structure is directly facing a top surface of the second semiconductor structure. A bonding layer is formed between the top surface of the first semiconductor structure and the top surface of the second semiconductor structure and the first wafer is bonded to the second wafer at a first temperature. The device is annealed at a second temperature to cure the bonding layer. The anneal temperature is greater than the bonding temperature.

公开(公告)号：US20230187496A1

公开(公告)日：2023-06-15

申请号：US17644463

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Shogo Mochizuki

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.

公开(公告)号：US20230094258A1

公开(公告)日：2023-03-30

申请号：US18061149

申请日：2022-12-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Koji Watanabe

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.

公开(公告)号：US11476418B2

公开(公告)日：2022-10-18

申请号：US17114605

申请日：2020-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  Ruqiang Bao ,  Andrew Herbert Simon ,  Kevin W. Brew ,  Nicole Saulnier ,  Iqbal Rashid Saraf ,  Prasad Bhosale

IPC: H01L45/00

Abstract: A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.