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1.
公开(公告)号:US20200212202A1
公开(公告)日:2020-07-02
申请号:US16799237
申请日:2020-02-24
发明人: Zhenxing Bi , Thamarai S. Devarajan , Balasubramanian Pranatharthiharan , Sanjay C. Mehta , Muthumanickam Sankarapandian
摘要: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
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2.
公开(公告)号:US20180226489A1
公开(公告)日:2018-08-09
申请号:US15425496
申请日:2017-02-06
发明人: Zhenxing Bi , Thamarai S. Devarajan , Balasubramanian Pranatharthiharan , Sanjay C. Mehta , Muthumanickam Sankarapandian
摘要: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
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3.
公开(公告)号:US11302797B2
公开(公告)日:2022-04-12
申请号:US16799237
申请日:2020-02-24
发明人: Zhenxing Bi , Thamarai S. Devarajan , Balasubramanian Pranatharthiharan , Sanjay C. Mehta , Muthumanickam Sankarapandian
IPC分类号: H01L29/66 , H01L29/06 , H01L29/49 , H01L29/78 , H01L29/786
摘要: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
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公开(公告)号:US09935015B1
公开(公告)日:2018-04-03
申请号:US15478822
申请日:2017-04-04
发明人: Zhenxing Bi , Donald F. Canaperi , Thamarai S. Devarajan , Sivananda K. Kanakasabapathy , Fee Li Lie , Peng Xu
IPC分类号: H01L21/31 , H01L21/76 , H01L21/311 , H01L21/762 , H01L29/66 , H01L29/06 , H01L29/78 , H01L21/8234
CPC分类号: H01L21/823481 , H01L21/0206 , H01L21/31111 , H01L21/31116 , H01L21/31138 , H01L21/76224 , H01L21/76229 , H01L21/823431 , H01L29/0649 , H01L29/0653 , H01L29/66795 , H01L29/7851
摘要: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.
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公开(公告)号:US09754798B1
公开(公告)日:2017-09-05
申请号:US15278747
申请日:2016-09-28
发明人: Zhenxing Bi , Donald F. Canaperi , Thamarai S. Devarajan , Sivananda K. Kanakasabapathy , Fee Li Lie , Peng Xu
IPC分类号: H01L21/31 , H01L21/76 , H01L29/66 , H01L29/06 , H01L21/311 , H01L21/762 , H01L29/78
CPC分类号: H01L21/823481 , H01L21/0206 , H01L21/31111 , H01L21/31116 , H01L21/31138 , H01L21/76224 , H01L21/76229 , H01L21/823431 , H01L29/0649 , H01L29/0653 , H01L29/66795 , H01L29/7851
摘要: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.
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6.
公开(公告)号:US09691765B1
公开(公告)日:2017-06-27
申请号:US15063735
申请日:2016-03-08
IPC分类号: H01L27/088 , H01L21/8234 , H01L21/02 , H01L21/311 , H01L29/06 , H01L27/02
CPC分类号: H01L21/823431 , H01L21/02274 , H01L21/31111 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L29/0649
摘要: A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.
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7.
公开(公告)号:US10388571B2
公开(公告)日:2019-08-20
申请号:US15982558
申请日:2018-05-17
IPC分类号: H01L21/8234 , H01L27/088 , H01L21/02 , H01L21/311 , H01L29/06 , H01L27/02 , H01L21/762 , H01L21/8238 , H01L27/092
摘要: A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.
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公开(公告)号:US10366928B2
公开(公告)日:2019-07-30
申请号:US15433163
申请日:2017-02-15
发明人: Zhenxing Bi , Donald F. Canaperi , Thamarai S. Devarajan , Sivananda K. Kanakasabapathy , Fee Li Lie , Peng Xu
IPC分类号: H01L21/8234 , H01L29/06 , H01L21/762 , H01L21/02 , H01L21/311 , H01L29/78 , H01L29/66
摘要: A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.
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公开(公告)号:US20190096669A1
公开(公告)日:2019-03-28
申请号:US15715559
申请日:2017-09-26
发明人: Zhenxing Bi , Thamarai S. Devarajan , Nicolas J. Loubet , Binglin Miao , Muthumanickam Sankarapandian , Charan V. Surisetty , Chun W. Yeung , Jingyun Zhang
IPC分类号: H01L21/02
摘要: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.
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10.
公开(公告)号:US10020229B2
公开(公告)日:2018-07-10
申请号:US15487685
申请日:2017-04-14
IPC分类号: H01L21/8234 , H01L27/088 , H01L21/02 , H01L21/311 , H01L29/06 , H01L27/02 , H01L21/762 , H01L21/8238 , H01L27/092
CPC分类号: H01L21/823431 , H01L21/02274 , H01L21/31111 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L29/0649
摘要: A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.
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