公开(公告)号：US20110014359A1

公开(公告)日：2011-01-20

申请号：US12921776

申请日：2009-04-17

申请人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

发明人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC分类号： B05D5/12

CPC分类号： H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

摘要翻译： 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）具有高介电常数和低泄漏特性的方法，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US08278735B2

公开(公告)日：2012-10-02

申请号：US12901239

申请日：2010-10-08

申请人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

发明人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC分类号： H01L21/02

CPC分类号： H01L28/40 ,  C23C14/083 ,  C23C14/3464 ,  C23C16/405 ,  C23C16/45531 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/0228

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

摘要翻译： 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US08900422B2

公开(公告)日：2014-12-02

申请号：US12921776

申请日：2009-04-17

申请人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

发明人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC分类号： B05D5/12 ,  C23C14/34 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108 ,  H01L21/02

CPC分类号： H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

摘要翻译： 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US20120061799A1

公开(公告)日：2012-03-15

申请号：US12901239

申请日：2010-10-08

申请人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

发明人： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC分类号： H01L29/92

CPC分类号： H01L28/40 ,  C23C14/083 ,  C23C14/3464 ,  C23C16/405 ,  C23C16/45531 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/0228

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

摘要翻译： 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，氧化物层可以通过PVD工艺或者通过使用特定前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产 反应。

公开(公告)号：US08449678B2

公开(公告)日：2013-05-28

申请号：US12028643

申请日：2008-02-08

申请人： Rick Endo ,  Kurt Weiner ,  Indranil De ,  James Tsung ,  Maosheng Zhao ,  Jeremy Cheng

发明人： Rick Endo ,  Kurt Weiner ,  Indranil De ,  James Tsung ,  Maosheng Zhao ,  Jeremy Cheng

IPC分类号： H01L21/31 ,  C23C16/458 ,  C23C16/50 ,  B65H1/00

CPC分类号： H01L21/32051 ,  B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00536 ,  B01J2219/00596 ,  B01J2219/00659 ,  B01J2219/00745 ,  B01J2219/00756 ,  C23C14/042 ,  C23C14/50 ,  C23C14/548 ,  C23C16/45544 ,  H01L21/67005 ,  H01L21/6719

摘要： A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

公开(公告)号：US07660687B1

公开(公告)日：2010-02-09

申请号：US11420243

申请日：2006-05-25

申请人： Indranil De ,  Mark A. McCord ,  David L. Adler

发明人： Indranil De ,  Mark A. McCord ,  David L. Adler

IPC分类号： G01D18/00 ,  G06F17/40 ,  G06F19/00

CPC分类号： H01J37/222 ,  G01R31/307 ,  H01J37/263 ,  H01J37/28 ,  H01J2237/2826

摘要： A method of increasing consistency between separate parametric measurement readings that are taken with an electron beam imaging tool at different times within a period of time, by correcting drift in the imaging tool at a time frequency that is less than a time period during which the drift is anticipated to be undesirably large.

摘要翻译： 一种提高在一段时间内在不同时间用电子束成像工具拍摄的单独的参数测量读数之间的一致性的方法，通过以小于漂移的时间段的时间频率校正成像工具中的漂移， 预计将不合需要。

公开(公告)号：US20090068849A1

公开(公告)日：2009-03-12

申请号：US11965689

申请日：2007-12-27

申请人： Rick Endo ,  Kurt Weiner ,  Indranil De ,  James Tsung ,  Maosheng Zhao

发明人： Rick Endo ,  Kurt Weiner ,  Indranil De ,  James Tsung ,  Maosheng Zhao

IPC分类号： H01L21/31 ,  C23C16/00

CPC分类号： C23C16/45565 ,  B05B14/30 ,  B05B16/80 ,  B05D1/10 ,  B05D1/62 ,  C23C16/4412 ,  C23C16/45589 ,  C23C16/4584 ,  C23C16/4585 ,  C23C16/4587 ,  C23C16/50 ,  Y10S438/942

摘要： The various embodiments of the invention provide for relative movement of the substrate and a process head to access the entire wafer in a minimal space to conduct combinatorial processing on various regions of the substrate. The heads enable site isolated processing within the chamber described and method of using the same are described.

摘要翻译： 本发明的各种实施例提供了基板和工艺头在最小空间中访问整个晶片的相对运动，以在基板的各个区域上进行组合处理。 这些头使得所描述的室内的现场隔离处理和使用其的方法被描述。

公开(公告)号：US08387563B2

公开(公告)日：2013-03-05

申请号：US13372729

申请日：2012-02-14

申请人： Rick Endo ,  Jeremy Cheng ,  Indranil De ,  James Tsung ,  Kurt Weiner ,  Maosheng Zhao

发明人： Rick Endo ,  Jeremy Cheng ,  Indranil De ,  James Tsung ,  Kurt Weiner ,  Maosheng Zhao

IPC分类号： H01L21/31 ,  C23C16/458 ,  C23C16/50 ,  B65H1/00

CPC分类号： H01L21/32051 ,  B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00536 ,  B01J2219/00596 ,  B01J2219/00659 ,  B01J2219/00745 ,  B01J2219/00756 ,  C23C14/042 ,  C23C14/50 ,  C23C14/548 ,  C23C16/45544 ,  H01L21/67005 ,  H01L21/6719

摘要： A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

公开(公告)号：US20090061087A1

公开(公告)日：2009-03-05

申请号：US12028643

申请日：2008-02-08

申请人： Rick Endo ,  Kurt Weiner ,  Indranil De ,  James Tsung ,  Maosheng Zhao ,  Jeremy Cheng

发明人： Rick Endo ,  Kurt Weiner ,  Indranil De ,  James Tsung ,  Maosheng Zhao ,  Jeremy Cheng

IPC分类号： C23C16/00

CPC分类号： H01L21/32051 ,  B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00536 ,  B01J2219/00596 ,  B01J2219/00659 ,  B01J2219/00745 ,  B01J2219/00756 ,  C23C14/042 ,  C23C14/50 ,  C23C14/548 ,  C23C16/45544 ,  H01L21/67005 ,  H01L21/6719

摘要： A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

公开(公告)号：US07280945B1

公开(公告)日：2007-10-09

申请号：US10187567

申请日：2002-07-01

申请人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

发明人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： G01R31/318364

摘要： Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e.g., due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e.g., a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection. Mechanisms for quickly inspecting such test structures to thereby predict systematic yield of a product device containing patterns similar to the test structure cells are also disclosed.

摘要翻译： 公开了提供用于确定特定集成电路（IC）模式是否易于系统故障（例如由于过程波动）的机制。 在一个实施例中，使用在各种处理设置下的稀疏型模拟器来模拟这种IC图案的最终抗蚀剂图案。 稀疏型模拟器对于要制造IC图案的特定光刻工艺使用模型（例如，可变阈值抗蚀剂模型）。 该模型是从从严格型模拟器输出的多个模拟结构中获得的测量产生的。 然后可以分析模拟的最终抗蚀剂图案，以确定相应的IC图案是否易于发生系统故障。 在已经发现容易发生系统故障的IC图案之后，可以从多个IC图案或单元制造测试结构。 测试结构的单元被布置成在电压对比度检查期间具有电压电位或亮度水平的特定图案。 还公开了用于快速检查这种测试结构从而预测包含类似于测试结构单元的图案的产品设备的系统产量的机制。