公开(公告)号：US20140312468A1

公开(公告)日：2014-10-23

申请号：US14033524

申请日：2013-09-23

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Yu-Chen Hsin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/30655 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a device layer and a least one conductive post. The substrate includes a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the substrate. The substrate includes a first side wall portion and a second side wall portion at the through hole. The first side wall portion is connected to the first surface and includes a plurality of first scallops. The second side wall portion is connected to the second surface and includes a non-scalloped surface. The device layer is disposed on the second surface, and the second side wall portion of the substrate further extends into the device layer along the non-scalloped surface. The conductive post is disposed in the through hole, wherein the conductive post is electrically connected to the device layer.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，器件层和至少一个导电柱。 衬底包括第一表面，与第一表面相对的第二表面和穿透衬底的至少一个通孔。 基板包括在通孔处的第一侧壁部分和第二侧壁部分。 第一侧壁部分连接到第一表面并且包括多个第一扇贝。 第二侧壁部分连接到第二表面并且包括非扇形表面。 器件层设置在第二表面上，并且衬底的第二侧壁部分还沿着非扇形表面延伸到器件层中。 导电柱设置在通孔中，其中导电柱电连接到器件层。

公开(公告)号：US09257337B2

公开(公告)日：2016-02-09

申请号：US14574348

申请日：2014-12-17

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Yu-Chen Hsin

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/822 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/80001

Abstract: A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括：提供具有第一有源表面和与第一有源表面相对的第一后表面的第一晶片，所述第一晶片包括形成在其中的第一电路; 提供具有第二有源表面和与所述第二有源表面相对的第二后表面的第二晶片，所述第二晶片包括形成在其中的第二电路; 将第一晶片的第一有源表面与第二晶片的第二有源表面接合，以便电连接第一电路和第二电路; 从第二后表面减薄第二晶片; 以及在所述第二晶片中至少形成导电通孔，其中所述导电通孔通过所述第二电路电连接到所述第一电路。

公开(公告)号：US09368475B2

公开(公告)日：2016-06-14

申请号：US14749644

申请日：2015-06-25

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L24/97 ,  H01L21/02304 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/145 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供一种半导体器件的制造方法。 首先，提供模具。 模具具有腔室，腔室中的图案和腔室中的突起。 具有位于其上的至少一个管芯的载体衬底设置在腔室中，并且突出部围绕模具。 将热固性材料注入室中并固化。 将固化的热固性材料与模具分离，以形成插入物基板。 对应于突起的多个通孔和对应于图案的多个槽形成在插入器基板上。 将导电材料填充到通孔和沟槽中以在内插器基板的第一表面上形成多个导电柱和第一导电图案层。 第一导电图案层与导电柱电连接。

公开(公告)号：US20140346666A1

公开(公告)日：2014-11-27

申请号：US14019548

申请日：2013-09-06

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes following steps. A mould is provided. The mould has a chamber and a plurality of protrusions in the chamber. A thermosetting material is injected into the chamber. The thermosetting material is cured. A parting step is performed to separate the cured thermosetting material from the mould, so as to form an interposer substrate. A plurality of blind holes corresponding to the protrusions is formed on the interposer substrate. A conductive material is filled into the blind holes to form a plurality of conductive pillars. A conductive pattern layer is formed on a surface of the interposer substrate. The conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供了一种半导体器件及其制造方法。 制造方法包括以下步骤。 提供模具。 模具在腔室中具有腔室和多个突起。 将热固性材料注入室中。 热固性材料固化。 执行分离步骤以将固化的热固性材料与模具分离，以形成插入物基板。 在内插基板上形成有与突起对应的多个盲孔。 将导电材料填充到盲孔中以形成多个导电柱。 导电图案层形成在中介层基板的表面上。 导电图案层与导电柱电连接。

公开(公告)号：US09093312B2

公开(公告)日：2015-07-28

申请号：US14019548

申请日：2013-09-06

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/04 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes following steps. A mold is provided. The mold has a chamber and a plurality of protrusions in the chamber. A thermosetting material is injected into the chamber. The thermosetting material is cured. A parting step is performed to separate the cured thermosetting material from the mold, so as to form an interposer substrate. A plurality of blind holes corresponding to the protrusions is formed on the interposer substrate. A conductive material is filled into the blind holes to form a plurality of conductive pillars. A conductive pattern layer is formed on a surface of the interposer substrate. The conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供了一种半导体器件及其制造方法。 制造方法包括以下步骤。 提供模具。 模具在腔室中具有腔室和多个突起。 将热固性材料注入室中。 热固性材料固化。 执行分离步骤以将固化的热固性材料与模具分离，以形成插入物基板。 在内插基板上形成有与突起对应的多个盲孔。 将导电材料填充到盲孔中以形成多个导电柱。 导电图案层形成在中介层基板的表面上。 导电图案层与导电柱电连接。

公开(公告)号：US20150104927A1

公开(公告)日：2015-04-16

申请号：US14574348

申请日：2014-12-17

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Yu-Chen Hsin

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/80001

Abstract: A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括：提供具有第一有源表面和与第一有源表面相对的第一后表面的第一晶片，所述第一晶片包括形成在其中的第一电路; 提供具有第二有源表面和与所述第二有源表面相对的第二后表面的第二晶片，所述第二晶片包括形成在其中的第二电路; 将第一晶片的第一有源表面与第二晶片的第二有源表面接合，以便电连接第一电路和第二电路; 从第二后表面减薄第二晶片; 以及在所述第二晶片中至少形成导电通孔，其中所述导电通孔通过所述第二电路电连接到所述第一电路。

公开(公告)号：US09257338B2

公开(公告)日：2016-02-09

申请号：US14615922

申请日：2015-02-06

Applicant: Industrial Technology Research Institute

Inventor： Chung-Chih Wang ,  Pei-Jer Tzeng ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/321 ,  H01L21/3213 ,  H01L25/00

CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/562 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/81 ,  H01L2224/8114 ,  H01L2224/81911 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Abstract translation: 本公开提供TSV衬底结构和多个衬底结构的层叠组件，TSV衬底结构包括：衬底，其包括第一表面，相应的第二表面以及将第一表面与第二表面通过第二表面连通的TSV 基质; 以及完全填充TSV的导体单元，所述导体单元包括分别具有对应于所述基板的第一和第二表面的第一端和第二端的导体本体。

公开(公告)号：US20150294953A1

公开(公告)日：2015-10-15

申请号：US14749644

申请日：2015-06-25

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L24/97 ,  H01L21/02304 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/145 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供一种半导体器件的制造方法。 首先，提供模具。 模具具有腔室，腔室中的图案和腔室中的突起。 具有位于其上的至少一个管芯的载体衬底设置在腔室中，并且突出部围绕模具。 将热固性材料注入室中并固化。 将固化的热固性材料与模具分离，以形成插入物基板。 对应于突起的多个通孔和对应于图案的多个槽形成在插入器基板上。 将导电材料填充到通孔和沟槽中以在内插器基板的第一表面上形成多个导电柱和第一导电图案层。 第一导电图案层与导电柱电连接。

公开(公告)号：US09041163B2

公开(公告)日：2015-05-26

申请号：US14033524

申请日：2013-09-23

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Yu-Chen Hsin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/30655 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a device layer and a least one conductive post. The substrate includes a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the substrate. The substrate includes a first side wall portion and a second side wall portion at the through hole. The first side wall portion is connected to the first surface and includes a plurality of first scallops. The second side wall portion is connected to the second surface and includes a non-scalloped surface. The device layer is disposed on the second surface, and the second side wall portion of the substrate further extends into the device layer along the non-scalloped surface. The conductive post is disposed in the through hole, wherein the conductive post is electrically connected to the device layer.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，器件层和至少一个导电柱。 衬底包括第一表面，与第一表面相对的第二表面和穿透衬底的至少一个通孔。 基板包括在通孔处的第一侧壁部分和第二侧壁部分。 第一侧壁部分连接到第一表面并且包括多个第一扇贝。 第二侧壁部分连接到第二表面并且包括非扇形表面。 器件层设置在第二表面上，并且衬底的第二侧壁部分还沿着非扇形表面延伸到器件层中。 导电柱设置在通孔中，其中导电柱电连接到器件层。

公开(公告)号：US20140238725A1

公开(公告)日：2014-08-28

申请号：US13778132

申请日：2013-02-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Erh-Hao Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H05K1/02 ,  H05K3/26

CPC classification number: H05K3/107 ,  H05K3/045 ,  H05K3/247 ,  H05K2201/0376 ,  H05K2203/025

Abstract: A method of flattening surface of conductive structure including a substrate, a dielectric layer on the substrate, and a conductive line formed in the dielectric layer is provided. A surface of the conductive line has a recess. A cover layer is formed on the substrate. A mechanical polishing process is performed to remove a portion of the cover layer. A remaining cover layer fills and levels the recess.

Abstract translation: 提供了包括基板，基板上的电介质层和形成在电介质层中的导电线的导电结构的表面平坦化的方法。 导线的表面具有凹部。 在基板上形成覆盖层。 执行机械抛光工艺以去除覆盖层的一部分。 剩余的覆盖层填充并平整凹部。