Abstract:
A silicon carbide device includes a transistor cell with a front side doping region, a body region, and a drift region. The body region includes a first portion having a first average net doping concentration and a second portion having a second average net doping concentration. The first portion and the second portion have an extension of at least 50 nm in a vertical direction. The first average net doping concentration is at least two times the second average net doping concentration, and the first average net doping concentration is at least 1·1017 cm−3.
Abstract:
The disclosure relates to a semiconductor device having a SiC semiconductor body. The SiC semiconductor body includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region is electrically contacted at a first surface of the SiC semiconductor body and forms a pn junction with the second semiconductor region. The first semiconductor region and the second semiconductor region are arranged one above the other in a vertical direction perpendicular to the first surface. The first semiconductor region has a first dopant species and a second dopant species.
Abstract:
A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Z1/2 defects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Z1/2 defects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.
Abstract:
A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.
Abstract:
A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.
Abstract:
A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone structure forms first pn junctions with body zones of the transistor cells. An auxiliary structure between the drift zone structure and a second surface at a rear side of the semiconductor body includes a first portion that contains deep level dopants requiring at least 150 meV to ionize. A collector structure directly adjoins the auxiliary structure. An injection efficiency of minority carriers from the collector structure into the drift zone structure varies along a direction parallel to the first surface at least in the transistor cell area.
Abstract:
A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.
Abstract:
Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm−3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm−3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.
Abstract:
A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.
Abstract:
A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.