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公开(公告)号：US20230178696A1
公开(公告)日：2023-06-08
申请号：US17540373
申请日：2021-12-02
Applicant: Infineon Technologies AG
Inventor： Dietrich Bonart , Alexander Heinrich , Bernhard Weidgans
IPC: H01L33/62 , H01L25/075
CPC classification number: H01L33/62 , H01L25/0753
Abstract: An optoelectronic assembly includes: a plurality of semiconductor light sources, each one of the semiconductor light sources including a plurality of pads; and a driver device configured to drive each one of the semiconductor light sources. For each pad of each semiconductor light source, the driver device has a corresponding pad facing the pad of the semiconductor light source to form a pair of connectable pads. For each pair of connectable pads, a first pad of the pair of connectable pads has a first shape and a second pad of the pair of connectable pads has a second shape complementary to the first shape such that the first pad and the second pad form a mated connection when brought into contact with one another. Corresponding driver device and semiconductor light sources are also described.
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公开(公告)号：US11127693B2
公开(公告)日：2021-09-21
申请号：US16710044
申请日：2019-12-11
Applicant: Infineon Technologies AG
Inventor： Johann Gatterbauer , Katrin Albers , Joerg Busch , Klaus Goller , Norbert Mais , Marianne Kolitsch , Michael Nelhiebel , Rainer Pelzer , Bernhard Weidgans
Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.
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3.发明申请
公开(公告)号：US20180350761A1
公开(公告)日：2018-12-06
申请号：US16101114
申请日：2018-08-10
Applicant: Infineon Technologies AG
Inventor： Manfred Schneegans , Franziska Haering , Hans-Joachim Schulze , Bernhard Weidgans
IPC: H01L23/00 , H01L21/768 , H01L23/532 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/739
CPC classification number: H01L24/05 , H01L21/76843 , H01L21/76858 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L24/03 , H01L29/407 , H01L29/417 , H01L29/41741 , H01L29/42376 , H01L29/45 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L2224/0345 , H01L2224/03462 , H01L2224/03848 , H01L2224/03912 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05611 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2924/13055 , H01L2924/13091 , H01L2924/3512 , H01L2924/00014 , H01L2924/01029 , H01L2924/01013 , H01L2924/01074
Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.
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公开(公告)号：US09887170B2
公开(公告)日：2018-02-06
申请号：US15592941
申请日：2017-05-11
Applicant: Infineon Technologies AG
Inventor： Manfred Schneegans , Bernhard Weidgans , Franziska Haering
CPC classification number: H01L24/06 , H01L21/0273 , H01L21/76864 , H01L21/76865 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/03462 , H01L2224/05087 , H01L2224/05093 , H01L2224/05098 , H01L2224/05147 , H01L2224/0603 , H01L2224/065 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45157 , H01L2224/45166 , H01L2224/45169 , H01L2224/45176 , H01L2224/45181 , H01L2224/45184 , H01L2224/48091 , H01L2224/48463 , H01L2224/4847 , H01L2224/48484 , H01L2224/49111 , H01L2224/49175 , H01L2224/85205 , H01L2224/85207 , H01L2924/1306 , H01L2924/35121 , H01L2924/00014
Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.
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公开(公告)号：US20170141090A1
公开(公告)日：2017-05-18
申请号：US14945170
申请日：2015-11-18
Applicant: Infineon Technologies AG
Inventor： Dietrich Bonart , Bernhard Weidgans , Johann Gatterbauer , Thomas Gross , Martina Heigl
IPC: H01L25/16 , H01L33/60 , H01L21/66 , H01L23/532 , H01L23/00 , H01L23/528 , H01L23/522 , H01L33/62 , H01L21/768
CPC classification number: H01L25/167 , H01L21/76834 , H01L21/76877 , H01L22/20 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/552 , H01L24/03 , H01L24/06 , H01L27/14692 , H01L31/055 , H01L33/20 , H01L33/405 , H01L33/46 , H01L33/60 , H01L33/62 , H01L2224/05144 , H01L2224/48227 , H01L2924/12041 , H01L2933/0058 , H01L2933/0066
Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.
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公开(公告)号：US11424201B2
公开(公告)日：2022-08-23
申请号：US16012341
申请日：2018-06-19
Applicant: Infineon Technologies AG
Inventor： Michael Rogalli , Johann Gatterbauer , Wolfgang Lehnert , Kurt Matoy , Evelyn Napetschnig , Manfred Schneegans , Bernhard Weidgans
IPC: H01L23/00
Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.
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公开(公告)号：US11164830B2
公开(公告)日：2021-11-02
申请号：US16153789
申请日：2018-10-07
Applicant: Infineon Technologies AG
Inventor： Dietrich Bonart , Ludger Borucki , Martina Debie , Bernhard Weidgans
IPC: H01L23/00
Abstract: Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.
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公开(公告)号：US10304782B2
公开(公告)日：2019-05-28
申请号：US15686576
申请日：2017-08-25
Applicant: Infineon Technologies AG
Inventor： Marianne Mataln , Michael Nelhiebel , Rainer Pelzer , Bernhard Weidgans
IPC: H01L23/00
Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the structured interlayer and also having defined edges. Each defined edge of the structured interlayer neighbors one of the defined edges of the structured metallization and runs in the same direction as the neighboring defined edge of the structured metallization. Each defined edge of the structured interlayer extends beyond the neighboring defined edge of the structured metallization by at least 0.5 microns so that each defined edge of the structured metallization terminates before reaching the neighboring defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature.
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9.发明申请
公开(公告)号：US20180366427A1
公开(公告)日：2018-12-20
申请号：US16012341
申请日：2018-06-19
Applicant: Infineon Technologies AG
Inventor： Michael Rogalli , Johann Gatterbauer , Wolfgang Lehnert , Kurt Matoy , Evelyn Napetschnig , Manfred Schneegans , Bernhard Weidgans
IPC: H01L23/00
Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.
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公开(公告)号：US20180308830A1
公开(公告)日：2018-10-25
申请号：US15974299
申请日：2018-05-08
Applicant: Infineon Technologies AG
Inventor： Dietrich Bonart , Bernhard Weidgans , Johann Gatterbauer , Thomas Gross , Martina Heigl
IPC: H01L25/16 , H01L23/552 , H01L27/146 , H01L33/46 , H01L23/00 , H01L31/055 , H01L33/60 , H01L21/768 , H01L33/62 , H01L23/528 , H01L33/40 , H01L23/532 , H01L23/522 , H01L33/20 , H01L21/66
CPC classification number: H01L25/167 , H01L21/76834 , H01L21/76877 , H01L22/20 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/552 , H01L24/03 , H01L24/06 , H01L27/14692 , H01L31/055 , H01L33/20 , H01L33/405 , H01L33/46 , H01L33/60 , H01L33/62 , H01L2224/05144 , H01L2224/48227 , H01L2924/12041 , H01L2933/0058 , H01L2933/0066
Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.
