公开(公告)号：US20240371772A1

公开(公告)日：2024-11-07

申请号：US18640821

申请日：2024-04-19

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Josef Schätz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L23/532 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SIC) semiconductor body including a trench structure. The trench structure extends into the SiC semiconductor body at a first surface of the SiC semiconductor body. The trench structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the SiC semiconductor body. An interlayer dielectric structure is arranged on the trench structure. The interlayer dielectric structure includes at least one of an aluminum nitride layer, a silicon nitride layer, an aluminum oxide layer, or a boron nitride layer. The vertical power semiconductor device further includes a source or emitter electrode on the interlayer dielectric structure.

公开(公告)号：US20240154020A1

公开(公告)日：2024-05-09

申请号：US18500635

申请日：2023-11-02

Applicant: Infineon Technologies AG

Inventor： Benedikt Stoib ,  Hans-Joachim Schulze ,  Marten Müller ,  Daniel Schlögl ,  Moriz Jelinek ,  Holger Schulze

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L29/66136 ,  H01L29/0615 ,  H01L29/8611

Abstract: A semiconductor device includes a semiconductor body having first and second opposite surfaces along a vertical direction, and an active diode area. The active diode area includes: a p-doped anode region adjoining the first surface; an n-doped drift region between the anode region and the second surface; an n-doped cathode contact region adjoining the second surface; a p-doped injection region adjoining the second surface and the cathode contact region; and a p-doped auxiliary region between the drift region and the cathode contact region. The auxiliary region includes first and second sub-regions. In a top view, the first sub-region covers at least part of the injection region and the second sub-region covers at least part of the cathode contact region. In the top view, the auxiliary region includes a plurality of openings covering from 0.1% to an 20% of a surface area of the active diode area at the second surface.

公开(公告)号：US11908694B2

公开(公告)日：2024-02-20

申请号：US17127309

申请日：2020-12-18

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Michael Hell ,  Caspar Leendertz ,  Kristijan Luka Mletschnig ,  Hans-Joachim Schulze

IPC: H01J37/317 ,  H01L21/265 ,  H01L21/04 ,  H01L29/36

CPC classification number: H01L21/26586 ,  H01J37/3171 ,  H01L21/046 ,  H01L21/047 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/36 ,  H01J2237/24578 ,  H01J2237/31703

Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.

公开(公告)号：US11764063B2

公开(公告)日：2023-09-19

申请号：US16886175

申请日：2020-05-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Romain Esteve ,  Moriz Jelinek ,  Caspar Leendertz ,  Werner Schustereder

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/047 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/7813

Abstract: A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.

公开(公告)号：US11735642B2

公开(公告)日：2023-08-22

申请号：US17314672

申请日：2021-05-07

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Roland Rupp ,  Francisco Javier Santos Rodriguez

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L21/683 ,  H01L21/04 ,  H01L21/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/66068 ,  H01L21/0262 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/02658 ,  H01L21/048 ,  H01L21/0475 ,  H01L21/6835 ,  H01L21/78 ,  H01L21/7806 ,  H01L21/7813 ,  H01L29/0804 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66053 ,  H01L29/7395 ,  H01L29/7802

Abstract: A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.

公开(公告)号：US11721547B2

公开(公告)日：2023-08-08

申请号：US13827253

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Christian Hecht ,  Tobias Hoechbauer ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/16

CPC classification number: H01L21/02529 ,  H01L21/76254 ,  H01L29/1608

Abstract: A method for manufacturing a silicon carbide substrate for an electrical silicon carbide device includes providing a silicon carbide dispenser wafer including a silicon face and a carbon face and depositing a silicon carbide epitaxial layer on the silicon face. Further, the method includes implanting ions with a predefined energy characteristic forming an implant zone within the epitaxial layer, so that the ions are implanted with an average depth within the epitaxial layer corresponding to a designated thickness of an epitaxial layer of the silicon carbide substrate to be manufactured. Furthermore, the method comprises bonding an acceptor wafer onto the epitaxial layer so that the epitaxial layer is arranged between the dispenser wafer and the acceptor wafer. Further, the epitaxial layer is split along the implant zone so that a silicon carbide substrate represented by the acceptor wafer with an epitaxial layer with the designated thickness is obtained.

公开(公告)号：US20230127556A1

公开(公告)日：2023-04-27

申请号：US17743006

申请日：2022-05-12

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Alexander Binter ,  Tobias Hoechbauer ,  Martin Huber ,  Iris Moder ,  Matteo Piccin ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/288 ,  H01L21/78

Abstract: A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non-porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.

公开(公告)号：US20230087353A1

公开(公告)日：2023-03-23

申请号：US17941052

申请日：2022-09-09

Applicant: Infineon Technologies AG

Inventor： Werner Schustereder ,  Roman Baburske ,  Hans-Joachim Schulze

IPC: H01L21/225 ,  H01L21/265 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/868 ,  H01L29/872

Abstract: A method of forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device includes: providing a semiconductor body; implanting a dopant to form a doped region in the semiconductor body; providing, above the doped region, a mask layer having a first section and a second section, the first section having has a first thickness along a vertical direction and the second section having a second thickness along the vertical direction, the second thickness being different from the first thickness; and subjecting the doped region and both mask sections to a laser thermal annealing, LTA, processing step.

公开(公告)号：US20220406947A1

公开(公告)日：2022-12-22

申请号：US17838339

申请日：2022-06-13

Applicant: Infineon Technologies AG

Inventor： Benedikt Stoib ,  Moriz Jelinek ,  Marten Mueller ,  Daniel Schloegl ,  Hans-Joachim Schulze ,  Holger Schulze

IPC: H01L29/861 ,  H01L29/36 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66

Abstract: A semiconductor device includes: a drift region of a first conductivity type arranged between first and second surfaces of a semiconductor body; a first region of the first conductivity type at the second surface; a second region of a second conductivity type adjacent the first region at the second surface; a field stop region of the first conductivity type between the drift region and second surface; and a first electrode on the second surface directly adjacent to the first region in a first part of the second surface and to the second region in a second part of the second surface. The field stop region includes first and second sub-regions. Over a predominant portion of the first part of the second surface, the second sub-region directly adjoins the first region and includes dopants of the second conductivity type that partially compensate dopants of the first conductivity type.

公开(公告)号：US11476111B2

公开(公告)日：2022-10-18

申请号：US16811192

申请日：2020-03-06

Applicant: Infineon Technologies AG

Inventor： Iris Moder ,  Bernhard Goller ,  Tobias Franz Wolfgang Hoechbauer ,  Roland Rupp ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L21/467

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.