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公开(公告)号：US20240298119A1
公开(公告)日：2024-09-05
申请号：US18177579
申请日：2023-03-02
发明人： Andreas Wiesbauer , Jose Luis Ceballos , Fulvio Ciciotti , Benno Muehlbacher , Maria Tzitzilaki , Mohammed Farag Nouraldin Hassan
CPC分类号： H04R19/005 , H03F3/187 , H04R3/06 , H03F2200/03 , H04R2201/003
摘要： In accordance with an embodiment, a circuit includes a differential amplifier having inputs configured to be coupled to an output of a differential microelectromechanical systems (MEMS) device; a common mode coupling circuit coupled to an output of the differential amplifier; and an amplifier having an input coupled to an output of the common mode coupling circuit and an output configured to be AC coupled to a bias input node of the differential MEMS device.
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公开(公告)号：US11929719B2
公开(公告)日：2024-03-12
申请号：US17658143
申请日：2022-04-06
CPC分类号： H03F3/183 , H04R3/00 , H04R19/04 , H03F2200/03 , H04R2201/003
摘要： In accordance with an embodiment, a circuit includes: a first super source follower; a compensation circuit having a compensating node configured to provide a voltage of opposite phase of a voltage of an internal node of the first super source follower; and a first compensation capacitor coupled between an input of the first super source follower and the compensating node of the compensation circuit.
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公开(公告)号：US20230328433A1
公开(公告)日：2023-10-12
申请号：US17658716
申请日：2022-04-11
CPC分类号： H04R3/02 , H03F3/45475 , H04R19/04 , H04R29/004 , H03F2200/03 , H04R2201/003
摘要： A single-ended to differential converter includes a converter input, a first converter output, a second converter output, and an internal node, wherein the first converter output and the second converter output comprise a differential output; a non-inverting amplifier having an input coupled to the converter input, and an output coupled to the first converter output; an inverting amplifier having an input coupled to the first converter output, and an output coupled to the second converter output; a charge pump having a charge pump output capacitor coupled between the second converter output and the internal node; and a feedback capacitor coupled between the first converter output and the internal node.
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公开(公告)号：US10194250B2
公开(公告)日：2019-01-29
申请号：US15383543
申请日：2016-12-19
IPC分类号： H04R19/04 , G01C19/5776 , G01P15/125 , H04R1/04 , H04R19/00 , H03F3/183 , H03F3/45 , H04R3/00
摘要： Methods and apparatuses are provided wherein a sensor which comprises at least two electrodes and a movable part is alternately biased with at least two different voltages.
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公开(公告)号：US20160065152A1
公开(公告)日：2016-03-03
申请号：US14935072
申请日：2015-11-06
CPC分类号： H03F3/183 , H03F1/32 , H03F1/56 , H03F3/187 , H03F2200/03 , H03F2200/105 , H03F2200/165 , H03F2200/211 , H03F2200/213 , H04R3/00 , H04R19/005 , H04R19/04
摘要： According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage.
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公开(公告)号：US20150334499A1
公开(公告)日：2015-11-19
申请号：US14811536
申请日：2015-07-28
CPC分类号： H04R29/004 , H04R3/00 , H04R3/007 , H04R19/005 , H04R19/016 , H04R19/04 , H04R2201/003
摘要： System and method for detecting a glitch is disclosed. An embodiment comprises increasing a bias voltage of a first capacitor, sampling an input signal of a first plate of the first capacitor with a time period, mixing the input signal with the sampled input signal, and comparing the mixed signal with a reference signal.
摘要翻译： 公开了用于检测毛刺的系统和方法。 实施例包括增加第一电容器的偏置电压，对时间周期对第一电容器的第一板的输入信号进行采样，将输入信号与采样的输入信号进行混合，以及将混合信号与参考信号进行比较。
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公开(公告)号：US20150180500A1
公开(公告)日：2015-06-25
申请号：US14138261
申请日：2013-12-23
摘要： In one embodiment the quantizer includes a signal-to-phase converter configured to generate a phase signal according to an input signal and a phase difference digitization block configured to generate a quantization output according to differentiated samples of the phase signal, where the phase signal generated by the signal-to-phase converter has a sinusoidal shape.
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公开(公告)号：US08947285B2
公开(公告)日：2015-02-03
申请号：US13795347
申请日：2013-03-12
发明人： Jose Luis Ceballos
摘要： Representative implementations of devices and techniques provide analog to digital conversion of analog inputs. A multistage comparator using a feed-forward technique can provide noise shaping of conversion errors. For example, the comparator may feed a conversion error forward from a first stage to a next stage of the multistage comparator.
摘要翻译： 设备和技术的代表性实现提供模拟输入的模数转换。 使用前馈技术的多级比较器可以提供转换误差的噪声整形。 例如，比较器可以将转换错误从第一级向下馈送到多级比较器的下一级。
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公开(公告)号：US20140140538A1
公开(公告)日：2014-05-22
申请号：US14163733
申请日：2014-01-24
CPC分类号： H03G7/08 , H03F1/3211 , H03F3/187 , H03F3/45475 , H03F2200/555 , H03F2203/45166 , H03F2203/45526 , H03G3/002 , H03G3/3005 , H03G3/3089 , H03G7/002 , H03G7/06 , H03K5/1532 , H03K5/1536 , H04R3/00 , H04R19/04 , H04R23/00 , H04R2201/003
摘要： In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block.
摘要翻译： 根据实施例，一种方法包括确定由电容信号源提供的输入信号的幅度，基于所确定的幅度压缩模拟域中的输入信号以形成压缩的模拟信号，将压缩的模拟信号转换为 压缩数字信号，并在数字域解压缩数字信号以形成解压缩的数字信号。 在一个实施例中，压缩模拟信号包括调整耦合到电容性信号源的放大器的第一增益，并且解压缩数字信号包括调整数字处理块的第二增益。
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公开(公告)号：US11750960B2
公开(公告)日：2023-09-05
申请号：US17451562
申请日：2021-10-20
CPC分类号： H04R1/08 , H03F3/183 , H03F2200/03 , H04R3/00 , H04R29/00
摘要： A microphone includes an amplifier coupled to an input node of the microphone; a shock detector coupled to the input node of the microphone; and a recovery circuit having an input coupled to an output of the shock detector, and an output coupled to the input of the microphone.
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