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    Compact Memory Arrays
    3.
    发明申请
    Compact Memory Arrays 失效
    紧凑型内存阵列

    公开(公告)号：US20130099289A1

    公开(公告)日：2013-04-25

    申请号：US13711404

    申请日：2012-12-11

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

    IPC: H01L23/52

    CPC classification number: H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

    Abstract translation: 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

    Circuit arrangement and method for operating a circuit arrangement
    5.
    发明授权
    Circuit arrangement and method for operating a circuit arrangement 有权
    用于操作电路装置的电路布置和方法

    公开(公告)号：US09123397B2

    公开(公告)日：2015-09-01

    申请号：US13969810

    申请日：2013-08-19

    Applicant: Infineon Technologies AG

    Inventor： Thomas Nirschl ,  Philipp Hofter

    IPC: G11C16/04 ,  G11C7/10 ,  G11C16/26 ,  G11C16/34 ,  H01L27/115

    CPC classification number: G11C7/10 ,  G11C7/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  H01L27/115

    Abstract: A circuit arrangement comprising a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and second access lines, the second access lines comprising at least two bit-lines; an access controller controlling access to at least one of the electronic components via the at least one first access line and the second access lines; and a first group of switches, wherein each switch comprises at least one control terminal and at least two controlled terminals. Each switch of the first group is connected to one of the at least two bit-lines via its control terminal and in a path between one first access line and a sense amplifier via its controlled terminals, and adjacent switches are connected via their control terminals to different bit-lines of the at least two bit-lines.

    Abstract translation: 一种电路装置，包括多个电子部件; 多个第一接入线路和第二接入线路，其中每个电子部件与至少一个第一接入线路和第二接入线路耦合，所述第二接入线路包括至少两个位线; 访问控制器，其经由所述至少一个第一接入线路和所述第二接入线路控制对所述电子部件中的至少一个的接入; 以及第一组开关，其中每个开关包括至少一个控制端子和至少两个受控端子。 第一组的每个开关经由其控制端子连接到至少两个位线中的一个，并且经由其受控端子连接到一个第一存取线路和读出放大器之间的路径中，并且相邻的开关经由其控制端子连接到 至少两个位线的不同位线。

    Compact memory arrays
    6.
    发明授权
    Compact memory arrays 失效
    紧凑型存储器阵列

    公开(公告)号：US08502276B2

    公开(公告)日：2013-08-06

    申请号：US13711404

    申请日：2012-12-11

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

    IPC: H01L23/52

    CPC classification number: H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

    Abstract translation: 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

    System and method to emulate an electrically erasable programmable read-only memory
    8.
    发明授权
    System and method to emulate an electrically erasable programmable read-only memory 有权
    用于模拟电可擦除可编程只读存储器的系统和方法

    公开(公告)号：US09569354B2

    公开(公告)日：2017-02-14

    申请号：US13957604

    申请日：2013-08-02

    Applicant: Infineon Technologies AG

    Inventor： Ulrich Backhausen ,  Thomas Kern ,  Thomas Nirschl ,  Jens Rosenbusch ,  Xiangting Bi ,  Edvin Paparisto

    IPC: G06F12/02 ,  G06F11/10 ,  G11C29/18

    CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C2029/1806

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

    Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于模拟电可擦除可编程只读存储器的系统，以及用于模拟电可擦除可编程只读存储器的方法。 根据本公开的实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，所述系统包括第一存储器部分和第二存储器部分，其中第一存储器部分包括多个存储位置，其被配置为存储 数据被分割成多个数据段，并且其中第二存储器部分被配置为存储将存储在第一存储器部分中的数据段的物理地址映射到数据段的逻辑地址的信息。

    Circuit arrangement and method for operating a circuit arrangement
    9.
    发明授权
    Circuit arrangement and method for operating a circuit arrangement 有权
    用于操作电路装置的电路布置和方法

    公开(公告)号：US09025391B2

    公开(公告)日：2015-05-05

    申请号：US13685737

    申请日：2012-11-27

    Applicant: Infineon Technologies AG

    Inventor： Thomas Nirschl ,  Christoph Roll ,  Philipp Hofter

    IPC: G11C7/10 ,  G11C5/14 ,  G11C7/02 ,  G11C16/12 ,  G11C16/04

    CPC classification number: G11C5/14 ,  G11C7/02 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12

    Abstract: A circuit arrangement, having a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and at least one second access line; an access controller configured to control an access to at least one electronic component of the plurality of electronic components via the at least one first access line and the at least one second access line; a bias circuit configured to provide a defined potential to at least one of the first access lines, wherein the bias circuit is configured, during an access to an electronic component via one selected first access line of the plurality of first access lines, to provide the defined potential to one or two first access lines of the plurality of first access lines, wherein the one or two first access lines are arranged adjacent to the selected first access line, and, wherein during the access to the electronic component, the potentials of the first access lines of the plurality of first access lines other than the selected first access line and the one or two first access lines arranged adjacent to the selected first access line are floating.

    Abstract translation: 一种电路装置，具有多个电子部件; 多个第一接入线路和第二接入线路，其中每个电子部件与至少一个第一接入线路和至少一个第二接入线路耦合; 访问控制器，被配置为经由所述至少一个第一接入线路和所述至少一个第二接入线路来控制对所述多个电子部件中的至少一个电子部件的访问; 偏置电路，被配置为：在通过所述多个第一接入线路中的所选择的第一接入线路访问电子部件期间，为所述第一接入线路中的至少一个提供限定的电位，其中所述偏置电路被配置， 所述多个第一接入线中的一个或两个第一接入线的限定电位，其中所述一个或两个第一接入线被布置为与所选择的第一接入线相邻，并且其中在所述电子部件的接入期间， 除了所选择的第一访问线路之外的多个第一访问线路中的第一接入线路和与所选择的第一接入线路相邻布置的一个或两个第一接入线路是浮动的。

    Circuit Arrangement and Method for Operating a Circuit Arrangement
    10.
    发明申请
    Circuit Arrangement and Method for Operating a Circuit Arrangement 有权
    电路布置和电路布置操作方法

    公开(公告)号：US20150049560A1

    公开(公告)日：2015-02-19

    申请号：US13969810

    申请日：2013-08-19

    Applicant: Infineon Technologies AG

    Inventor： Thomas Nirschl ,  Philipp Hofter

    IPC: G11C7/10

    CPC classification number: G11C7/10 ,  G11C7/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  H01L27/115

    Abstract: A circuit arrangement comprising a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and second access lines, the second access lines comprising at least two bit-lines; an access controller controlling access to at least one of the electronic components via the at least one first access line and the second access lines; and a first group of switches, wherein each switch comprises at least one control terminal and at least two controlled terminals. Each switch of the first group is connected to one of the at least two bit-lines via its control terminal and in a path between one first access line and a sense amplifier via its controlled terminals, and adjacent switches are connected via their control terminals to different bit-lines of the at least two bit-lines.

    Abstract translation: 一种电路装置，包括多个电子部件; 多个第一接入线路和第二接入线路，其中每个电子部件与至少一个第一接入线路和第二接入线路耦合，所述第二接入线路包括至少两个位线; 访问控制器，其经由所述至少一个第一接入线路和所述第二接入线路控制对所述电子部件中的至少一个的接入; 以及第一组开关，其中每个开关包括至少一个控制端子和至少两个受控端子。 第一组的每个开关经由其控制端子连接到至少两个位线中的一个，并且经由其受控端子连接到一个第一存取线路和读出放大器之间的路径中，并且相邻的开关经由其控制端子连接到 至少两个位线的不同位线。

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