-
公开(公告)号：US10553557B2
公开(公告)日：2020-02-04
申请号：US14533520
申请日：2014-11-05
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing , Marcus Pawley , Andrew Roberts , Robert Clarke
IPC: H05K3/30 , H01L25/065
Abstract: In an embodiment, an electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact layer protruding from a first side face of the dielectric core layer. The contact layer includes an electrically insulating layer and at least one contact pad arranged on the electrically insulating layer. The at least one contact pad is electrically coupled with the power semiconductor device.
-
公开(公告)号：US10257937B2
公开(公告)日：2019-04-09
申请号：US14324316
申请日：2014-07-07
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing , Andrew Roberts
IPC: H05K1/18 , H01L21/288 , H01L21/768 , H01L23/48 , H01L23/00 , H01L25/065 , H01L25/16 , H01L25/00 , H05K13/04 , H05K1/14 , H01L23/538 , H01L23/13 , H01L23/498 , H05K1/11 , H05K1/02
Abstract: An assembly includes a first laminate electronic component and a second laminate electronic component. The first laminate electronic component includes a first dielectric layer, at least one first semiconductor die embedded in the first dielectric layer and at least one first contact pad including a first conductive via. The second laminate electronic component includes a second dielectric layer, at least one second semiconductor die embedded in the second dielectric layer and at least one second contact pad including a second conductive via. The first conductive via is electrically coupled to the second conductive via by a common conductive layer.
-
公开(公告)号：US09974190B2
公开(公告)日：2018-05-15
申请号：US14533448
申请日：2014-11-05
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing , Andrew Roberts
Abstract: In an embodiment, a method includes arranging a first carrier on a first major surface of a circuit board such that an electronic component arranged on the first carrier is positioned in an aperture in the circuit board and spaced apart from side walls of the aperture, and arranging a second carrier on a second major surface of the circuit board such that the second carrier covers the electronic component and the aperture, the second major surface of the circuit board opposing the first major surface of the circuit board. The electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact pad arranged on a first major surface of the dielectric core layer.
-
公开(公告)号：US20170317005A1
公开(公告)日：2017-11-02
申请号：US15655202
申请日：2017-07-20
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing
IPC: H01L23/367 , H01L23/373 , H01L23/538 , H01L23/433
CPC classification number: H01L23/367 , H01L23/373 , H01L23/3733 , H01L23/4334 , H01L23/5389 , H01L2224/04105 , H01L2224/06181 , H01L2224/2518 , H01L2224/73267 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091
Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and a heat-sink thermally coupled to the heat-spreader. The heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor devices.
-
公开(公告)号：US20170154856A1
公开(公告)日：2017-06-01
申请号：US15343041
申请日：2016-11-03
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing
CPC classification number: H01L23/562 , H01L23/051 , H01L23/3107 , H01L23/3114 , H01L23/3135 , H01L23/3157 , H01L24/27 , H01L24/30 , H01L29/7827 , H01L2224/04105 , H01L2224/2518 , H01L2224/28105 , H01L2224/29005
Abstract: In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, the semiconductor die having a first surface and a thickness t1. A second dielectric layer is arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition, and a conductive layer is arranged on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The conductive layer has a thickness t2, wherein t2≧t1/3.
-
6.发明申请Electronic component and method for dissipating heat from a semiconductor die 审中-公开用于从半导体管芯散热的电子部件和方法
公开(公告)号：US20160005673A1
公开(公告)日：2016-01-07
申请号：US14324779
申请日：2014-07-07
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing , Marcus Pawley
IPC: H01L23/367 , H01L21/56 , H01L23/373 , H01L23/00 , H01L23/31 , H01L23/48
CPC classification number: H01L23/367 , H01L21/56 , H01L23/051 , H01L23/145 , H01L23/3107 , H01L23/3114 , H01L23/36 , H01L23/481 , H01L23/49562 , H01L23/49844 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/19 , H01L24/32 , H01L2224/0502 , H01L2224/32057 , H01L2224/32245 , H01L2224/73267 , H01L2924/13055 , H01L2924/13091 , H05K1/185 , H01L2924/00
Abstract: In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.
Abstract translation: 在一个实施例中，电子部件包括具有厚度的介电芯层，至少一个半导体管芯嵌入在介电芯层中并电耦合到布置在介电芯层的第一侧上的至少一个接触焊盘， 散热层布置在介质芯层的第二侧上并热耦合到半导体管芯。 半导体管芯具有基本上等于或大于或等于介电芯层的厚度的厚度。 散热层包括具有基本上各向同性导热性的材料。
-
公开(公告)号：US20150078042A1
公开(公告)日：2015-03-19
申请号：US14031720
申请日：2013-09-19
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing
IPC: H05K7/20
CPC classification number: H05K7/2089 , H02M1/4208 , H02M5/4585 , H02M7/003 , H02M7/06 , H02M7/219 , H05K1/0206 , H05K1/0209 , H05K7/209 , H05K2201/10189
Abstract: A power supply includes a plurality of electronic components including one or more of a rectifier and a switching transistor, an input port configured to receive electrical energy from a power source and a circuit board comprising a cavity. At least one of the rectifier and the switching transistor is embedded in the cavity. The cavity is arranged proximal to the input port such that at least a portion of thermal energy generated by one or more of the rectifier and the switching transistor is dissipated from the power supply by way of the input port.
Abstract translation: 电源包括包括整流器和开关晶体管中的一个或多个的多个电子部件，被配置为从电源接收电能的输入端口和包括空腔的电路板。 整流器和开关晶体管中的至少一个嵌入在空腔中。 空腔布置在输入端口附近，使得由整流器和开关晶体管中的一个或多个产生的至少一部分热能通过输入端口从电源消散。
-
公开(公告)号：US10074616B2
公开(公告)日：2018-09-11
申请号：US15343041
申请日：2016-11-03
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing
IPC: H01L23/00 , H01L23/31 , H01L29/78 , H01L23/051
CPC classification number: H01L23/562 , H01L23/051 , H01L23/3107 , H01L23/3114 , H01L23/3135 , H01L23/3157 , H01L24/20 , H01L24/27 , H01L24/30 , H01L29/7827 , H01L2224/04105 , H01L2224/2518 , H01L2224/28105 , H01L2224/29005
Abstract: In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, the semiconductor die having a first surface and a thickness t1. A second dielectric layer is arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition, and a conductive layer is arranged on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The conductive layer has a thickness t2, wherein t2≥t1/3.
-
9.发明授权
公开(公告)号：US09917024B2
公开(公告)日：2018-03-13
申请号：US15210752
申请日：2016-07-14
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing , Marcus Pawley
IPC: H01L23/04 , H01L21/48 , H01L23/498 , H01L23/538 , H01L23/00 , H01L23/36
CPC classification number: H01L23/04 , H01L21/4803 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L23/36 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/49844 , H01L23/5384 , H01L23/5389 , H01L24/06 , H01L24/25 , H01L2224/04105 , H01L2224/06181 , H01L2224/2518 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153
Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.
-
公开(公告)号：US20170196118A1
公开(公告)日：2017-07-06
申请号：US15464384
申请日：2017-03-21
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing
CPC classification number: H05K7/2089 , H02M1/4208 , H02M5/4585 , H02M7/003 , H02M7/06 , H02M7/219 , H05K1/0206 , H05K1/0209 , H05K7/209 , H05K2201/10189
Abstract: A power supply includes a plurality of electronic components including one or more of a rectifier and a switching transistor, an input port configured to receive electrical energy from a power source and a circuit board comprising a cavity. At least one of the rectifier and the switching transistor is embedded in the cavity. The cavity is arranged proximal to the input port such that at least a portion of thermal energy generated by one or more of the rectifier and the switching transistor is dissipated from the power supply by way of the input port.
