公开(公告)号：US09250831B1

公开(公告)日：2016-02-02

申请号：US14194574

申请日：2014-02-28

Applicant: INPHI CORPORATION

Inventor： Nirmal Raj Saxena ,  Sreenivas Krishnan ,  David Wang

IPC: G06F12/10 ,  G06F3/06 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0644 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0813 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.

Abstract translation: 大规模并行和以内存为中心的计算系统的技术。 该系统具有通过一个或多个通信信道彼此可操作地耦合的多个处理单元。 多个处理单元中的每一个具有ISMn接口装置。 多个ISMn接口设备中的每一个耦合到连接到每个处理单元的ISMe端点。 该系统具有以分解体系结构配置的多个DRAM或闪存，以及可操作地以分解结构耦合多个DRAM或闪速存储器的一个或多个交换节点。 该系统具有多个高速光缆，其配置为以100G或更大的传输速率进行通信，以便于从多个处理单元中的任何一个到多个DRAM或闪存中的任何一个的通信。

公开(公告)号：US08996960B1

公开(公告)日：2015-03-31

申请号：US13797583

申请日：2013-03-12

Applicant: Inphi Corporation

Inventor： Nirmal Raj Saxena ,  David Wang ,  Hamid Rategh ,  Lawrence Tse

IPC: G11C29/00 ,  H03M13/17

CPC classification number: H03M13/17 ,  G06F11/1048

Abstract: Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.

Abstract translation: 操作DIMM装置的技术。 该装置包括从0到N-1编号的多个DRAM器件，其中N是大于7（7）的整数，每个DRAM器件被配置在衬底模块中; 包括从0到N-1编号的多个数据缓冲器（DB）的缓冲器集成电路器件，其中N是大于7（7）的整数，每个数据缓冲器对应于一个DRAM器件; 以及与多个DRAM设备相关联的多个纠错模块（“ECM”）。

公开(公告)号：US09015558B2

公开(公告)日：2015-04-21

申请号：US14228847

申请日：2014-03-28

Applicant: Inphi Corporation

Inventor： David Wang ,  Christopher Haywood

IPC: G11C29/00 ,  G06F11/10 ,  G11C7/10 ,  G11C11/408 ,  G11C29/52 ,  H03M13/15 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G11C7/1006 ,  G11C11/408 ,  G11C29/52 ,  G11C29/848 ,  G11C2029/0411 ,  H03M13/1515 ,  H03M13/152

Abstract: The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.

Abstract translation: 本系统包括存储模块，该存储器模块包含多个RAM芯片，通常为DRAM，以及一个存储器缓冲器，用于缓冲DRAM和主机控制器之间的数据。 存储器缓冲器包括错误检测和校正电路，其布置成确保存储的数据字的完整性。 可以实现这一点的一种方式是通过计算每个数据字的奇偶校验位并将它们与每个数据字并行存储。 如果主机控制器包括自己的错误检测和校正电路，则可以将错误检测和校正电路设置为检测和纠正单个错误或多个错误。 或者，可以确定故障存储单元的位置并将其存储在地址匹配表中，该地址匹配表然后被用于控制将故障单元周围的数据引导到冗余DRAM芯片或在另一实施例中的嵌入式SRAM。

公开(公告)号：US09142279B2

公开(公告)日：2015-09-22

申请号：US14242292

申请日：2014-04-01

Applicant: INPHI CORPORATION

Inventor： David Wang

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40607 ,  G11C11/40618

Abstract: A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times.

Abstract translation: DRAM刷新方法与存储器系统一起使用，存储器系统被组织成行的存储器单元，每个存储器单元具有相关的数据保留时间，系统被布置为同时刷新存储器单元的预定义块。 对于要同时刷新的每个存储单元块，确定块中存储单元的最小数据保留时间。 然后，创建不对称刷新序列，其指定刷新存储器单元的块的顺序，使得具有最短最小数据保留时间的块比具有较长最小数据保留时间的块更频繁地刷新。

公开(公告)号：US08854908B1

公开(公告)日：2014-10-07

申请号：US13797814

申请日：2013-03-12

Applicant: Inphi Corporation

Inventor： Andrew Burstein ,  David Wang

IPC: G11C29/00 ,  G11C29/52

CPC classification number: G11C29/52 ,  G11C5/04 ,  G11C29/44 ,  G11C29/846

Abstract: A random access memory includes a plurality of memories configured to store and provide data, and a test module coupled to the plurality of memories, wherein the test module is configured to write a first write data pattern into at last a first portion of the plurality of memories in response to a data pattern value, wherein the test module is configured to read a read data pattern from the plurality of memories, wherein the test module is configured to compare the first write data pattern to the read data pattern, and wherein the test module is configured to report errors in response to a comparison of the write data pattern to the read data pattern.

Abstract translation: 随机存取存储器包括被配置为存储和提供数据的多个存储器以及耦合到所述多个存储器的测试模块，其中所述测试模块被配置为将第一写入数据模式写入到所述多个存储器的第一部分 响应于数据模式值的存储器，其中所述测试模块被配置为从所述多个存储器读取读取数据模式，其中所述测试模块被配置为将所述第一写入数据模式与所读取的数据模式进行比较，并且其中所述测试 模块被配置为响应于写数据模式与读数据模式的比较来报告错误。

公开(公告)号：US09349433B2

公开(公告)日：2016-05-24

申请号：US14175857

申请日：2014-02-07

Applicant: INPHI CORPORATION

Inventor： David Wang

IPC: G11C8/00 ,  G11C11/4063 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/4063 ,  G11C11/40611 ,  G11C11/4076

Abstract: In an example, the present invention provides a computing system. The system has a memory interface device comprising a counter, a dynamic random access memory device coupled to the memory interface device. The device comprises a plurality of banks, each of the banks having a subarray, each subarray having a plurality of memory cells. The device has a data interface coupled to the plurality of banks. The device has an address interface coupled to the plurality of banks, and a particular pre-charge command configured to be transferred to the memory interface device. The counter is adapted to count a measured time duration from a first time when data are available at the data interface to a second time when a pre-charge command is received by the address interface.

Abstract translation: 在一个示例中，本发明提供一种计算系统。 该系统具有包括计数器，耦合到存储器接口设备的动态随机存取存储器设备的存储器接口设备。 该设备包括多个存储体，每个存储体具有子阵列，每个子阵列具有多个存储单元。 该设备具有耦合到多个存储体的数据接口。 该设备具有耦合到多个存储区的地址接口，以及被配置为传送到存储器接口设备的特定预充电命令。 该计数器适于对数据接口上的数据可用的第一次计数到第二次当地址接口接收到预充电命令时的测量持续时间。

公开(公告)号：US09317366B2

公开(公告)日：2016-04-19

申请号：US14593257

申请日：2015-01-09

Applicant: INPHI CORPORATION

Inventor： David Wang

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/00 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G06F11/008 ,  G06F11/1004 ,  G06F11/1016 ,  G06F12/00

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

公开(公告)号：US09239355B1

公开(公告)日：2016-01-19

申请号：US13786325

申请日：2013-03-05

Applicant: Inphi Corporation

Inventor： Andrew Burstein ,  Larry Kan ,  Chien-Hsin Lee ,  Srinivas Bamdhamravuri ,  David Wang

IPC: G06F19/00 ,  G01R31/26 ,  G06F17/00

CPC classification number: G11C29/16 ,  G11C5/04 ,  G11C11/401

Abstract: An interface device for a memory module comprising a plurality of DRAMs includes a memory configured to store DRAM test program instructions, and a programmable processing device coupled to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions.

Abstract translation: 包括多个DRAM的存储器模块的接口装置包括被配置为存储DRAM测试程序指令的存储器和耦合到存储器的可编程处理设备，其中可编程处理设备被配置为从一个或多个存储器地址接收输入数据和输入存储器地址 外部处理器，其中所述可编程处理设备被配置为向所述多个DRAM提供数据和存储器地址，并且其中所述可编程处理设备被编程为执行由所述DRAM测试程序指令指定的操作。

公开(公告)号：US09170878B2

公开(公告)日：2015-10-27

申请号：US13791124

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： Christopher Haywood ,  David Wang

IPC: G06F11/10 ,  G11C7/10 ,  G06F11/07 ,  G11C29/04

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract translation: 一种用于操作DRAM设备的方法。 该方法包括在由计算系统托管的第一存储器模块中的存储器缓冲器中接收从计算系统的主机控制器存储在第一存储器模块的RAM中的数据的请求。 该方法包括响应于该请求而与RAM相关联的数据与存储缓冲器一起接收，响应于伪随机过程将该数据转换成加扰数据。 该方法包括利用存储缓冲器启动加扰数据到接口设备中。

公开(公告)号：US09348539B1

公开(公告)日：2016-05-24

申请号：US14194416

申请日：2014-02-28

Applicant: INPHI CORPORATION

Inventor： Nirmal Raj Saxena ,  David Wang ,  Christopher Haywood ,  Eric McDonald ,  Chao Xu

IPC: G06F3/06

CPC classification number: G11C11/005 ,  G11C5/04

Abstract: A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.

Abstract translation: 混合存储器系统。 该系统可以包括耦合到耦合到多个DRAM和多个闪存模块的混合存储器缓冲器（HMB）的处理器。 HMB模块可以包括由SerDes（串行器/解串器）接口耦合的存储器存储控制器（MSC）模块和近端存储器处理（NMP）模块。 该系统可以利用混合（混合存储器型）存储器系统架构，其适用于在用于工业标准计算机系统的相同存储器子系统中支持低延迟DRAM设备和低成本NAND闪存器件。