公开(公告)号：US12068319B2

公开(公告)日：2024-08-20

申请号：US16141000

申请日：2018-09-25

申请人： INTEL CORPORATION

发明人： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66537 ,  H01L29/6659

摘要： Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US11950407B2

公开(公告)日：2024-04-02

申请号：US16828507

申请日：2020-03-24

申请人： Intel Corporation

发明人： Juan G. Alzate Vinasco ,  Travis W. Lajoie ,  Abhishek A. Sharma ,  Kimberly L Pierce ,  Elliot N. Tan ,  Yu-Jin Chen ,  Van H. Le ,  Pei-Hua Wang ,  Bernhard Sell

IPC分类号： H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC分类号： H10B12/315 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/91 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/318 ,  H10B12/482 ,  H10B12/485

摘要： Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240098965A1

公开(公告)日：2024-03-21

申请号：US17933589

申请日：2022-09-20

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

IPC分类号： H01L27/108 ,  G11C5/06 ,  G11C5/10 ,  H01L23/48 ,  H01L25/065 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/11514

CPC分类号： H01L27/10876 ,  G11C5/063 ,  G11C5/10 ,  H01L23/481 ,  H01L25/0655 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/11514 ,  H01L27/10826 ,  H01L27/10879

摘要： Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

公开(公告)号：US20240088029A1

公开(公告)日：2024-03-14

申请号：US17930841

申请日：2022-09-09

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Sagar Suthram

IPC分类号： H01L23/528 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L23/5226

摘要： Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.

公开(公告)号：US20240055531A1

公开(公告)日：2024-02-15

申请号：US18494384

申请日：2023-10-25

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC分类号： H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H10B12/00

CPC分类号： H01L29/78642 ,  H01L29/78648 ,  H01L29/0847 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/78696 ,  H01L29/1037 ,  H01L21/02647 ,  H01L29/6656 ,  H01L29/42384 ,  H10B12/05 ,  H10B12/50 ,  H10B12/315 ,  H01L21/31116

摘要： Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US20230420409A1

公开(公告)日：2023-12-28

申请号：US17846086

申请日：2022-06-22

申请人： Intel Corporation

发明人： Sagar Suthram ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L24/94 ,  H01L2224/80896 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L24/97

摘要： Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

公开(公告)号：US20230420363A1

公开(公告)日：2023-12-28

申请号：US18314875

申请日：2023-05-10

申请人： Intel Corporation

发明人： Sagar Suthram ,  Elliot Tan ,  Abhishek A. Sharma ,  Shem Odhiambo Ogadhoh ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L23/528 ,  H01L27/092

CPC分类号： H01L23/528 ,  H01L27/0924

摘要： IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

公开(公告)号：US20230413547A1

公开(公告)日：2023-12-21

申请号：US17843867

申请日：2022-06-17

申请人： Intel Corporation

发明人： Sagar Suthram ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Pushkar Sharad Ranade

IPC分类号： H01L27/1156 ,  H01L27/11524

CPC分类号： H01L27/1156 ,  H01L27/11524

摘要： IC devices implementing 2T memory cells with source-drain coupling in one transistor, and related assemblies and methods, are disclosed herein. In particular, 2T memory cells presented herein use first and second transistors arranged so that source and drain terminals of the second transistor are coupled to one another. A memory state may be represented by charge indicative of the bit value stored in the second transistor, while the first transistor may serve as a switch to control access to the second transistor. 2T memory cells with source-drain coupling in one transistor provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

公开(公告)号：US11832438B2

公开(公告)日：2023-11-28

申请号：US16457634

申请日：2019-06-28

申请人： Intel Corporation

发明人： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Jared Stoeger ,  Yu-Wen Huang ,  Shu Zhou

IPC分类号： H10B12/00 ,  H01L27/12 ,  H01L49/02

CPC分类号： H10B12/315 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L28/82 ,  H10B12/0335 ,  H10B12/312

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20230307291A1

公开(公告)日：2023-09-28

申请号：US17656366

申请日：2022-03-24

申请人： Intel Corporation

发明人： Moshe Dolejsi ,  Harish Ganapathy ,  Travis W. Lajoie ,  Deepyanti Taneja ,  Huiying Liu ,  Cheng Tan ,  Timothy Jen ,  Van H. Le ,  Abhishek A. Sharma

IPC分类号： H01L21/768 ,  H01L27/108 ,  H01L23/522

CPC分类号： H01L21/76829 ,  H01L21/76859 ,  H01L23/5226 ,  H01L27/10852

摘要： An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.