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公开(公告)号:US10317938B2
公开(公告)日:2019-06-11
申请号:US14604531
申请日:2015-01-23
申请人: Intel Corporation
发明人: Eng Huat Goh , Khai Ern See , Damien Weng Kong Chong , Min Suet Lim , Ping Ping Ooi , Chu Aun Lim , Jimmy Huat Since Huang , Poh Tat Oh , Teong Keat Beh , Jackson Chung Peng Kong , Fern Nee Tan , Jenn Chuan Cheng
摘要: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.
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公开(公告)号:US20170359893A1
公开(公告)日:2017-12-14
申请号:US15182091
申请日:2016-06-14
申请人: Intel Corporation
发明人: Eng Huat Goh , Min Suet Lim , Fern Nee Tan , Khang Choong Yong , Jiun Hann Sir
IPC分类号: H05K1/02 , H01G4/008 , H01L23/00 , H01G4/12 , H01L21/48 , H05K1/18 , H05K1/11 , H01G4/30 , H05K1/09 , H01L23/498
CPC分类号: H05K1/0231 , H01G4/1209 , H01G4/228 , H01G4/33 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/48227 , H01L2924/01022 , H01L2924/01028 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/15311 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/15763 , H01L2924/19041 , H01L2924/19102 , H05K1/141 , H05K2201/10015 , H05K2201/10378 , H05K2201/10734
摘要: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops. The capacitive interconnects can be utilized in a semiconductor package, providing a compact assembly that can reduce the utilization of real estate in a board substrate onto which the semiconductor package is mounted.
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公开(公告)号:US10560094B2
公开(公告)日:2020-02-11
申请号:US15670740
申请日:2017-08-07
申请人: Intel Corporation
IPC分类号: H03K3/012 , H03K19/003 , H01L23/64 , H01L23/00
摘要: An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.
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公开(公告)号:US20220300048A1
公开(公告)日:2022-09-22
申请号:US17712010
申请日:2022-04-01
申请人: Intel Corporation
发明人: Min Suet Lim , Jeff Ku , Fern Nee Tan , John Lang , Kavitha Nagarajan , Javed Shaikh , Deepak Sekar
IPC分类号: G06F1/20 , G06F1/16 , H01L23/373 , H05K1/02 , H05K7/20
摘要: Thermal Management Systems for electronic devices and related methods are disclosed. An example electronic housing includes a housing defining a cavity, electronics in the cavity, and a touch display over the electronics. A heat spreader has a first surface toward the electronics and a second surface opposite the first surface toward the touch display, where the heat spreader is to dissipate heat generated by the electronics. A glass cover is coupled to the housing and has a first side toward the touch display and a second side opposite the first side, where the glass cover is exposed external to the housing. An insulation layer is between the second surface of the heat spreader and the second side of the glass cover to restrict heat transfer from the electronics to the second side of the glass cover.
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公开(公告)号:US20210385942A1
公开(公告)日:2021-12-09
申请号:US16988759
申请日:2020-08-10
申请人: Intel Corporation
发明人: Tai Loong Wong , Fern Nee Tan , Tin Poay Chuah , Min Suet Lim , Siang Yeong Tan
摘要: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.
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公开(公告)号:US20160216731A1
公开(公告)日:2016-07-28
申请号:US14604531
申请日:2015-01-23
申请人: Intel Corporation
发明人: Eng Huat Goh , Khai Ern See , Damien Weng Kong Chong , Min Suet Lim , Ping Ping Ooi , Chu Aun Lim , Jimmy Huat Since Huang , Poh Tat Oh , Teong Keat Beh , Jackson Chung Peng Kong , Fern Nee Tan , Jenn Chuan Cheng
CPC分类号: G06F1/163 , G06F1/16 , G06F1/1656 , G06F1/187 , G06F13/38 , H01L2224/16225 , H01L2224/48091 , H01L2224/73204 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.
摘要翻译: 实施例一般涉及利用计算机在包装结构上的装置。 计算机的一个实施例包括基板; 一个或多个半导体器件,所述一个或多个半导体器件是直接芯片附着到所述衬底,所述一个或多个半导体器件包括中央处理单元(CPU); 以及安装在基板上的一个或多个附加部件,其中计算机不包括I / O部件。
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公开(公告)号:US11343906B2
公开(公告)日:2022-05-24
申请号:US16988759
申请日:2020-08-10
申请人: Intel Corporation
发明人: Tai Loong Wong , Fern Nee Tan , Tin Poay Chuah , Min Suet Lim , Siang Yeong Tan
摘要: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.
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公开(公告)号:US10609813B2
公开(公告)日:2020-03-31
申请号:US15182091
申请日:2016-06-14
申请人: Intel Corporation
发明人: Eng Huat Goh , Min Suet Lim , Fern Nee Tan , Khang Choong Yong , Jiun Hann Sir
摘要: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.
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公开(公告)号:US20170338820A1
公开(公告)日:2017-11-23
申请号:US15670740
申请日:2017-08-07
申请人: Intel Corporation
IPC分类号: H03K19/003 , H01L23/64 , H01L23/00
CPC分类号: H03K19/00346 , H01L23/645 , H01L24/13 , H01L24/16 , H01L2223/6688 , H01L2224/131 , H01L2224/16227 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , Y10T307/406 , H01L2924/014
摘要: An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.
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公开(公告)号:US09729151B2
公开(公告)日:2017-08-08
申请号:US14046592
申请日:2013-10-04
申请人: Intel Corporation
IPC分类号: H03K3/012 , H03K19/003 , H01L23/64 , H01L23/00
CPC分类号: H03K19/00346 , H01L23/645 , H01L24/13 , H01L24/16 , H01L2223/6688 , H01L2224/131 , H01L2224/16227 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , Y10T307/406 , H01L2924/014
摘要: An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.
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