公开(公告)号：US10205292B2

公开(公告)日：2019-02-12

申请号：US15716356

申请日：2017-09-26

申请人： INTEL CORPORATION

发明人： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC分类号： H01R33/76 ,  H01L23/32 ,  H01L23/498

摘要： Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20170354031A1

公开(公告)日：2017-12-07

申请号：US15172102

申请日：2016-06-02

申请人： Intel Corporation

发明人： Russell S. Aoki ,  Jeffory L. Smalley ,  Jonathan W. Thibado

IPC分类号： H05K1/02 ,  H01L23/00 ,  H01L25/065 ,  H05K1/14 ,  H05K3/36 ,  H05K1/18 ,  H05K3/34 ,  H01L23/498 ,  G06F1/16

CPC分类号： H05K1/0271 ,  G06F1/16 ,  G06F1/206 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15323 ,  H05K1/0212 ,  H05K1/144 ,  H05K1/181 ,  H05K3/341 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/10189 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10734

摘要： An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.

公开(公告)号：US09490560B2

公开(公告)日：2016-11-08

申请号：US14576735

申请日：2014-12-19

申请人： INTEL CORPORATION

发明人： Gaurav Chawla ,  David J. Llapitan ,  Jeffory L. Smalley ,  Tejinder Pal Aulakh ,  Vijaykumar Krithivasan ,  Donald T. Tran

IPC分类号： H01R12/79 ,  H05K7/10 ,  H01R43/20 ,  G06F1/18

CPC分类号： H01R12/79 ,  G06F1/18 ,  H01R43/205 ,  H05K7/1069 ,  H05K7/1092

摘要： A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.

摘要翻译： 描述了使用弹簧偏压的多阵列底侧阵列的连接器。 在一个示例中，连接器包括连接器壳体，连接器壳体具有底表面，以及与底表面相对的多个弹性连接器，以电连接到集成电路封装的对应的多个焊盘;电缆连接器，用于电连接 电缆的弹性连接器，具有压靠电路板的底表面的基板和与底表面相对的顶表面，以及联接在基板和连接器底表面之间的多个弹簧构件，用于将基板 底部表面靠在系统板上，并将连接器外壳连接件按压在包装上。

公开(公告)号：US20160181714A1

公开(公告)日：2016-06-23

申请号：US14576735

申请日：2014-12-19

申请人： INTEL CORPORATION

发明人： GAURAV CHAWLA ,  David J. Llapitan ,  Jeffory L. Smalley ,  Tejinder Pal Aulakh ,  Vijaykumar Krithivasan ,  Donald T. Tran

IPC分类号： H01R12/79 ,  H05K7/10 ,  G06F1/18 ,  H01R43/20

CPC分类号： H01R12/79 ,  G06F1/18 ,  H01R43/205 ,  H05K7/1069 ,  H05K7/1092

摘要： A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.

摘要翻译： 描述了使用弹簧偏压的多阵列底侧阵列的连接器。 在一个示例中，连接器包括连接器壳体，连接器壳体具有底表面，以及与底表面相对的多个弹性连接器，以电连接到集成电路封装的对应的多个焊盘;电缆连接器，用于电连接 电缆的弹性连接器，具有压靠电路板的底表面的基板和与底表面相对的顶表面，以及联接在基板和连接器底表面之间的多个弹簧构件，用于将基板 底部表面靠在系统板上，并将连接器外壳连接件按压在包装上。

公开(公告)号：US20160118315A1

公开(公告)日：2016-04-28

申请号：US14918119

申请日：2015-10-20

申请人： Intel Corporation

发明人： Susan F. Smith ,  Jeffory L. Smalley ,  Mani Prakash ,  Thu Huynh

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

CPC分类号： H01L23/3672 ,  H01L21/4882 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/427 ,  H01L25/065 ,  H01L25/50 ,  H01L2023/4037 ,  H01L2023/4056 ,  H01L2023/4068 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the primary device and having an opening over an area corresponding to the at least one secondary device; a second heat exchanger disposed in the opening on the at least one secondary device; at least one heat pipe coupled to the first heat exchanger and the second heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including a first portion, a second portion and at least one heat pipe coupled to the first portion and the second portion; and coupling the heat exchanger to the multi-chip package.

摘要翻译： 一种装置，包括主要装置和至少一个辅助装置，其以平面阵列耦合到基板; 第一热交换器，其设置在所述主装置上并且在对应于所述至少一个次装置的区域上具有开口; 设置在所述至少一个次要装置的开口中的第二热交换器; 耦合到第一热交换器和第二热交换器的至少一个热管。 一种方法，包括将热交换器放置在多芯片封装上，所述热交换器包括耦合到所述第一部分和所述第二部分的第一部分，第二部分和至少一个热管; 并将热交换器耦合到多芯片封装。

公开(公告)号：US11545408B2

公开(公告)日：2023-01-03

申请号：US16249499

申请日：2019-01-16

申请人： Intel Corporation

发明人： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh

IPC分类号： H01L23/34 ,  H05K1/02 ,  H01L23/36 ,  H01L23/498 ,  H01L21/50 ,  H01L21/48 ,  H05K1/18 ,  H05K1/11

摘要： Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a substrate having vias and zones, where the zones have embedded heaters. The heaters may include first traces, second traces, and via filament interconnects. The vias may have a z-height greater than a z-height of the heaters, and each of the zones may have a grid pattern. The RGA interposer may include first and second layers in the substrate, where the first layer includes the first traces, the second layer includes the second traces, and the second layer is over the first layer. The grid pattern may have parallel first traces orthogonal to parallel second traces to form a pattern of squares, where the pattern of squares has the first traces intersect the second traces substantially at right angles.

公开(公告)号：US20210120668A1

公开(公告)日：2021-04-22

申请号：US17111424

申请日：2020-12-03

申请人： Intel Corporation

发明人： Russell S. Aoki ,  Jeffory L. Smalley ,  Jonathan W. Thibado

IPC分类号： H05K1/02 ,  G06F1/20 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H05K3/34 ,  G06F1/16

摘要： An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.

公开(公告)号：US10211120B2

公开(公告)日：2019-02-19

申请号：US14998123

申请日：2015-12-23

申请人： Intel Corporation

发明人： Russell S. Aoki ,  Jonathan W. Thibado ,  Jeffory L. Smalley ,  David J. Llapitan ,  Thomas A. Boyd ,  Harvey R. Kofstad ,  Dimitrios Ziakas ,  Hongfei Yan

IPC分类号： H01L23/34 ,  H01L23/498 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34

摘要： A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.

公开(公告)号：US09832876B2

公开(公告)日：2017-11-28

申请号：US14575775

申请日：2014-12-18

申请人： INTEL CORPORATION

发明人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC分类号： H05K1/18 ,  H01L23/00 ,  H01R12/71 ,  H01R12/79

CPC分类号： H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

公开(公告)号：US09806003B2

公开(公告)日：2017-10-31

申请号：US15197129

申请日：2016-06-29

申请人： Intel Corporation

发明人： Jeffory L. Smalley ,  Susan F. Smith ,  Thu Huynh ,  Mani Prakash

IPC分类号： H01L23/42 ,  H01L25/00 ,  H05K1/02 ,  H05K7/20 ,  H01L23/427 ,  H01L25/065

CPC分类号： H01L23/427 ,  H01L23/3672 ,  H01L23/473 ,  H01L25/0655 ,  H01L25/50 ,  H05K1/0203 ,  H05K7/20336 ,  H05K7/20409 ,  H05K7/20509 ,  H05K2201/10522

摘要： An apparatus including a primary device and at least one secondary device coupled to a substrate; a heat exchanger disposed on the primary device and on the at least one secondary device, wherein the heat exchanger includes at least one portion disposed over an area corresponding to the primary device or the at least one second device including a deflectable surface; and at least one thermally conductive conduit coupled to the heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including the heat exchanger including at least one floating section operable to move in a direction toward or away from at least one of the plurality of dice and at least one thermally conductive conduit disposed in a channel of the heat exchanger and connected to the at least one floating section; and coupling the heat exchanger to the multi-chip package.