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公开(公告)号：US10748242B2
公开(公告)日：2020-08-18
申请号：US16046650
申请日：2018-07-26
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G09G5/00 , G06T1/60 , G06F12/0875 , G06T1/20
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US20180286011A1
公开(公告)日：2018-10-04
申请号：US15477039
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G06T1/60 , G06T1/20 , G06F12/0875
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US20220414977A1
公开(公告)日：2022-12-29
申请号：US17357423
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Ronald Silvas , Karol A. Szerszen
Abstract: Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.
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公开(公告)号：US11080925B2
公开(公告)日：2021-08-03
申请号：US16456645
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
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公开(公告)号：US20210142438A1
公开(公告)日：2021-05-13
申请号：US16683024
申请日：2019-11-13
Applicant: Intel Corporation
Inventor： Abhishek R. APPU , Eric G. LISKAY , Prasoonkumar SURTI , Sudhakar KAMMA , Karthik VAIDYANATHAN , Rajasekhar PANTANGI , Altug KOKER , Abhishek RHISHEEKESAN , Shashank LAKSHMINARAYANA , Priyanka LADDA , Karol A. Szerszen
Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.
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公开(公告)号：US12243155B2
公开(公告)日：2025-03-04
申请号：US17357423
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Ronald Silvas , Karol A. Szerszen
Abstract: Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.
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公开(公告)号：US11574382B2
公开(公告)日：2023-02-07
申请号：US17466591
申请日：2021-09-03
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Eric G. Liskay , Prasoonkumar Surti , Sudhakar Kamma , Karthik Vaidyanathan , Rajasekhar Pantangi , Altug Koker , Abhishek Rhisheekesan , Shashank Lakshminarayana , Priyanka Ladda , Karol A. Szerszen
Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.
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公开(公告)号：US20210035259A1
公开(公告)日：2021-02-04
申请号：US16930935
申请日：2020-07-16
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G06T1/60 , G06F12/0875 , G06T1/20
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US20200098167A1
公开(公告)日：2020-03-26
申请号：US16456645
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
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公开(公告)号：US20160086374A1
公开(公告)日：2016-03-24
申请号：US14492173
申请日：2014-09-22
Applicant: Intel Corporation
Inventor： Robert L. Farrell , Prasoonkumar Surti , Vasanth Ranganathan , Karol A. Szerszen
CPC classification number: G06T15/405 , G06T5/002 , G06T9/00 , G06T11/40
Abstract: By packing the depth data in a way that is independent of the number of samples, so that memory bandwidth is the same regardless of the number of samples, higher numbers of samples per pixel may be used without adversely affecting buffer cost. In some embodiments, the number of pixels per clock in a first level depth test may be increased by operating in the pixel domain, whereas previous solutions operated at the sample level.
Abstract translation: 通过以独立于样本数量的方式打包深度数据，使得存储器带宽相同，而不考虑样本数量，可以使用每像素更多的采样数，而不会不利地影响缓冲器成本。 在一些实施例中，可以通过在像素域中操作来增加第一级深度测试中每个时钟的像素数量，而先前的解决方案在采样级别下运行。
