公开(公告)号：US20240385884A1

公开(公告)日：2024-11-21

申请号：US18571092

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Zhongyan Lu

IPC: G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to estimate workload complexity. An example apparatus includes processor circuitry to perform at least one of first, second, or third operations to instantiate payload interface circuitry to extract workload objective information and service level agreement (SLA) criteria corresponding to a workload, and acceleration circuitry to select a pre-processing model based on (a) the workload objective information and (b) feedback corresponding to workload performance metrics of at least one prior workload execution iteration, execute the pre-processing model to calculate a complexity metric corresponding to the workload, and select candidate resources based on the complexity metric.

公开(公告)号：US12132790B2

公开(公告)日：2024-10-29

申请号：US17875672

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Patrick Bohan ,  Kshitij Arun Doshi ,  Brinda Ganesh ,  Andrew J. Herdrich ,  Monica Kenguva ,  Karthik Kumar ,  Patrick G Kutch ,  Felipe Pastor Beneyto ,  Rashmin Patel ,  Suraj Prabhakaran ,  Ned M. Smith ,  Petar Torre ,  Alexander Vul

IPC: H04L67/148 ,  G06F9/48 ,  H04L41/5003 ,  H04L41/5019 ,  H04L43/0811 ,  H04L47/70 ,  H04L67/00 ,  H04L67/10 ,  H04W4/40 ,  H04W4/70

CPC classification number: H04L67/148 ,  G06F9/4856 ,  H04L41/5019 ,  H04L43/0811 ,  H04L47/82 ,  H04L67/10 ,  H04L67/34 ,  H04W4/40 ,  H04W4/70 ,  H04L41/5003

Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes. In a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.

公开(公告)号：US20240179578A1

公开(公告)日：2024-05-30

申请号：US18427242

申请日：2024-01-30

Applicant: Intel Corporation

Inventor： Akhilesh Shivanna Thyagaturu ,  Hassnaa Moustafa Ep. Yehia ,  Jing Zhu ,  Karthik Kumar ,  Shu-Ping Yeh ,  Henning Schroeder ,  Menglei Zhang ,  Mohit Kumar Garg ,  Shiva Radhakrishnan Iyer ,  Francesc Guim Bernat

IPC: H04W28/26 ,  H04W28/02 ,  H04W28/084

CPC classification number: H04W28/26 ,  H04W28/0268 ,  H04W28/084

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to manage network slices. An example apparatus includes interface circuitry to acquire network information, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to reserve first network slices to satisfy service level objectives (SLOs) corresponding to first nodes, reserve second network slices to satisfy SLOs corresponding to second nodes, and reconfigure the first network slices to accept network communications from the second nodes when the network communications from the second nodes exceed a performance metric threshold.

公开(公告)号：US11994997B2

公开(公告)日：2024-05-28

申请号：US17132431

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark A. Schmisseur

IPC: G11C16/04 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/0882 ,  G06F13/16

CPC classification number: G06F12/0882 ,  G06F9/5016 ,  G06F12/0238 ,  G06F12/0835 ,  G06F13/1668 ,  G06F2209/5011 ,  G06F2209/504 ,  G06F2209/508

Abstract: Systems, apparatuses and methods may provide for a memory controller to manage quality of service enforcement and migration between local and pooled memory. A memory controller may include logic to communicate with a local memory and with a pooled memory controller to track memory page usage on a per application basis, instruct the pooled memory controller to perform a quality of service enforcement in response to a determination that an application is latency bound or bandwidth bound, wherein the determination that the application is latency bound or bandwidth bound is based on a cycles per instruction determination, and instruct a Direct Memory Access engine to perform a migration from a remote memory to the local memory in response to a determination that the quality of service cannot be enforced.

公开(公告)号：US11994932B2

公开(公告)日：2024-05-28

申请号：US16907264

申请日：2020-06-21

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods and apparatus for platform ambient data management schemes for tiered architectures. A platform including one or more CPUs coupled to multiple tiers of memory comprising various types of DIMMs (e.g., DRAM, hybrid, DCPMM) is powered by a battery subsystem receiving input energy harvested from one or more green energy sources. Energy threshold conditions are detected, and associated memory reconfiguration is performed. The memory reconfiguration may include but is not limited to copying data between DIMMs (or memory ranks on the DIMMS in the same tier, copying data between a first type of memory to a second type of memory on a hybrid DIMM, and flushing dirty lines in a DIMM in a first memory tier being used as a cache for a second memory tier. Following data copy and flushing operations, the DIMMs and/or their memory devices are powered down and/or deactivated. In one aspect, machine learning models trained on historical data are employed to project harvested energy levels that are used in detecting energy threshold conditions.

公开(公告)号：US11907136B2

公开(公告)日：2024-02-20

申请号：US16820630

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Ginger H. Gilsdorf ,  Karthik Kumar ,  Mark A. Schmisseur ,  Thomas Willhalm ,  Francesc Guim Bernat

IPC: G06F12/123 ,  G06F12/0891 ,  G11C7/22 ,  G06F1/14 ,  G06F12/02

CPC classification number: G06F12/123 ,  G06F1/14 ,  G06F12/0246 ,  G06F12/0891 ,  G11C7/22

Abstract: An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

公开(公告)号：US20230412699A1

公开(公告)日：2023-12-21

申请号：US18456102

申请日：2023-08-25

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L67/51 ,  H04L41/5009 ,  H04L9/32 ,  H04L67/562

CPC classification number: H04L67/51 ,  H04L41/5009 ,  H04L9/3278 ,  H04L67/562 ,  H04L9/50

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to obtain provenance metadata for a microservice from a local blockchain of provenance metadata maintained for the hardware resource executing a task performed by the microservice, the provenance metadata comprising identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and an operating state of a sidecar of the microservice during the task; access one or more policies established for the microservice; analyze the provenance metadata with respect to the one or more policies to identify if there is a violation of the one or more policies; and generate one or more evaluation metrics based on whether the violation of the one or more policies is identified.

公开(公告)号：US20230199077A1

公开(公告)日：2023-06-22

申请号：US18067097

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L67/51 ,  H04L67/562 ,  H04L41/5009 ,  H04L9/32

CPC classification number: H04L67/51 ,  H04L67/562 ,  H04L41/5009 ,  H04L9/3278 ,  H04L9/50

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to: obtain, by a microservice of a service hosted in a datacenter, provisioned credentials for the microservice based on an attestation protocol; generate, for a task performed by the microservice, provenance metadata for the task, the provenance metadata including identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and operating state of a sidecar of the microservice during the task; encrypt the provenance metadata with the provisioned credentials for the microservice; and record the encrypted provenance metadata in a local blockchain of provenance metadata maintained for the hardware resource executing the task and the microservice.

公开(公告)号：US20230029026A1

公开(公告)日：2023-01-26

申请号：US17958140

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Andrzej Kuriata ,  Duane Galbi

IPC: G06F13/40 ,  H04L67/2866

Abstract: A network processing device connects to one or more devices in a computing node and connects to one or more other network processing devices of other computing nodes. The network processing device identifies a policy for allowing devices in other computing nodes to access a particular resource of one of the devices in its computing node. The network processing device receives an access request to access the particular resource from another network processing device and sends a request to the device hosting the particular resource based on the access request and the policy.

公开(公告)号：US20220200788A1

公开(公告)日：2022-06-23

申请号：US17561558

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Rajesh Poornachandran ,  Kapil Sood ,  Tarun Viswanathan ,  John J. Browne ,  Patrick Kutch

IPC: H04L9/08

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.