公开(公告)号：US09747971B2

公开(公告)日：2017-08-29

申请号：US14955012

申请日：2015-11-30

申请人： Intel Corporation

发明人： Kuljit S Bains ,  John B Halbert ,  Christopher P Mozak ,  Theodore Z Schoenborn ,  Zvika Greenfield

IPC分类号： G06F12/10 ,  G11C11/406 ,  G11C11/4091

CPC分类号： G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US20160225433A1

公开(公告)日：2016-08-04

申请号：US14955012

申请日：2015-11-30

申请人： Intel Corporation

发明人： Kuljit S Bains ,  John B Halbert ,  Christopher P Mozak ,  Theodore Z Schoenborn ,  Zvika Greenfield

IPC分类号： G11C11/406 ,  G11C11/4091

CPC分类号： G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

摘要翻译： 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中被重复访问时，物理上相邻的行（“受害者”行）可能经历数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：US10127101B2

公开(公告)日：2018-11-13

申请号：US14998184

申请日：2015-12-26

申请人： Intel Corporation

发明人： John B Halbert ,  Kuljit S Bains

IPC分类号： H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/09 ,  G11C29/42 ,  G11C11/401

摘要： An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

公开(公告)号：US09811420B2

公开(公告)日：2017-11-07

申请号：US14670413

申请日：2015-03-27

申请人： Intel Corporation

发明人： Debaleena Das ,  Bill Nale ,  Kuljit S Bains ,  John B Halbert

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

摘要： Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

公开(公告)号：US09780782B2

公开(公告)日：2017-10-03

申请号：US14498794

申请日：2014-09-26

申请人： Intel Corporation

发明人： Kuljit S Bains ,  Nadav Bonen

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G06F13/40

CPC分类号： H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

摘要： A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US20160196866A1

公开(公告)日：2016-07-07

申请号：US15068925

申请日：2016-03-14

申请人： INTEL CORPORATION

发明人： Kuljit S Bains

IPC分类号： G11C11/406

CPC分类号： G11C11/40615 ,  G06F12/02 ,  G06F13/1636 ,  G11C2211/4067

摘要： Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

摘要翻译： 本发明的实施例描述了一种动态随机存取存储器（DRAM）装置，其可以中止自刷新模式以改善从自动刷新的DRAM低功率状态的退出时间。 在执行自刷新模式期间，DRAM设备可以从可操作地耦合到DRAM设备的存储器控​​制器接收信号（例如，器件使能信号）。 响应于接收到来自存储器控制器的信号，DRAM设备可以中止自刷新模式。

公开(公告)号：US09817714B2

公开(公告)日：2017-11-14

申请号：US14998142

申请日：2015-12-26

申请人： Intel Corporation

发明人： John B Halbert ,  Kuljit S Bains ,  Kjersten E Criss

IPC分类号： G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/09 ,  H03M13/00 ,  G11C29/42 ,  G11C11/401

CPC分类号： G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

摘要： In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

公开(公告)号：US09728245B2

公开(公告)日：2017-08-08

申请号：US14865754

申请日：2015-09-25

申请人： Intel Corporation

发明人： Kuljit S Bains ,  John B Halbert ,  Nadav Bonen ,  Tomer Levy

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

摘要： Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

公开(公告)号：US09721643B2

公开(公告)日：2017-08-01

申请号：US15170606

申请日：2016-06-01

申请人： Intel Corporation

发明人： Kuljit S Bains ,  John B Halbert

IPC分类号： G06F12/12 ,  G11C11/4078 ,  G06F13/16 ,  G11C11/406 ,  G11C11/408 ,  G11C29/50 ,  G11C29/04

CPC分类号： G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

摘要： Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

公开(公告)号：US20160378366A1

公开(公告)日：2016-12-29

申请号：US14749605

申请日：2015-06-24

申请人： Intel Corporation

发明人： Shigeki Tomishima ,  Shih-Lien L. Lu ,  Kuljit S Bains

IPC分类号： G06F3/06 ,  G11C15/00 ,  G11C7/10

CPC分类号： G11C7/1072 ,  G11C7/08 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1045 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/409

摘要： A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.

摘要翻译： 存储器件执行内部操作以提供可编程突发长度。 存储器件包括独立且可单独寻址的多个存储体。 存储器设备选择多个存储体以突发序列操作，其中所有选择的存储体根据从相关联的存储器控​​制器发送的命令进行操作。 响应于接收到访问命令，存储器设备生成多个内部操作以使得所有选择的存储体执行访问命令，而不需要来自存储器控制器的多个命令。