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1.发明授权公开(公告)号：US11106271B2
公开(公告)日：2021-08-31
申请号：US16572747
申请日：2019-09-17
Applicant: Intel Corporation
Inventor： Alexander Gendler , Arkady Bramnik , Lev Makovsky
IPC: G06F1/32 , G06F1/3287 , G06F11/10 , G06F1/324 , G06F1/3234 , G06F1/3296
Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.
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2.发明申请
公开(公告)号：US20200012333A1
公开(公告)日：2020-01-09
申请号：US16572747
申请日：2019-09-17
Applicant: Intel Corporation
Inventor： Alexander Gendler , Arkady Bramnik , Lev Makovsky
IPC: G06F1/3287 , G06F1/324 , G06F11/10
Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.
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公开(公告)号：US20210271305A1
公开(公告)日：2021-09-02
申请号：US17183518
申请日：2021-02-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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4.发明授权
公开(公告)号：US10437315B2
公开(公告)日：2019-10-08
申请号：US15629872
申请日：2017-06-22
Applicant: Intel Corporation
Inventor： Alexander Gendler , Arkady Bramnik , Lev Makovsky
IPC: G06F1/32 , G06F1/3287 , G06F11/10 , G06F1/324 , G06F1/3234 , G06F1/3296
Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.
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公开(公告)号：US20180173298A1
公开(公告)日：2018-06-21
申请号：US15381611
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Alexander Gendler , Boris Mishori , Krishnakanth V. Sistla , Ankush Varma , Avinash N. Ananthakrishnan , Lev Makovsky , Michael Zelikson , Eran Altshuler , Israel Stolero
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/3206 , G06F1/324
Abstract: An apparatus is provided, comprising: a first circuitry configured to generate a signal at a voltage level for one or more components; a second circuitry configured to generate a clock at a frequency level for the one or more components; a third circuitry configured to intermittently measure a current level of the signal; a fourth circuitry configured to estimate a first average of the current level of the signal over a first time-window; and a fifth circuitry configured to, in response to the first average being higher than a threshold average current, facilitate regulating one or both the voltage level of the signal or the frequency level of the clock.
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公开(公告)号：US11385704B2
公开(公告)日：2022-07-12
申请号：US17183518
申请日：2021-02-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/32 , G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US20200310511A1
公开(公告)日：2020-10-01
申请号：US16369793
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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8.发明申请
公开(公告)号：US20180373315A1
公开(公告)日：2018-12-27
申请号：US15629872
申请日：2017-06-22
Applicant: Intel Corporation
Inventor： Alexander Gendler , Arkady Bramnik , Lev Makovsky
CPC classification number: G06F1/3287 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F11/1004 , G06F11/1076
Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.
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9.发明授权
公开(公告)号：US09292362B2
公开(公告)日：2016-03-22
申请号：US13926089
申请日：2013-06-25
Applicant: Intel Corporation
Inventor： Lev Makovsky , Zeev Sperber , Efraim Rotem , Nir Rosenzweig , Stanislav Shwartsman , Raanan Sade , Igor Yanover , Gavri Berger , Tomer Weiner , Ron Gabor
CPC classification number: G06F9/542 , G06F1/3206 , G06F9/30 , G06F9/4856 , Y02D10/24 , Y02D10/32
Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。
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公开(公告)号：US10936041B2
公开(公告)日：2021-03-02
申请号：US16369793
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/32 , G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
