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公开(公告)号：US11841752B2
公开(公告)日：2023-12-12
申请号：US17338547
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Tessil Thomas , Lokesh Sharma , Buck Gremel , Ian Steiner
IPC: G06F1/20 , G06F1/3234
CPC classification number: G06F1/206 , G06F1/3243 , Y02D10/00
Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
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公开(公告)号：US20210294400A1
公开(公告)日：2021-09-23
申请号：US17338547
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Tessil Thomas , Lokesh Sharma , Buck Gremel , Ian Steiner
IPC: G06F1/20 , G06F1/3234
Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
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公开(公告)号：US20190107872A1
公开(公告)日：2019-04-11
申请号：US16215978
申请日：2018-12-11
Applicant: Intel Corporation
Inventor： Tessil Thomas , Lokesh Sharma , Buck Gremel , Ian Steiner
IPC: G06F1/20 , G06F1/3234
Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
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公开(公告)号：US11079819B2
公开(公告)日：2021-08-03
申请号：US16215978
申请日：2018-12-11
Applicant: Intel Corporation
Inventor： Tessil Thomas , Lokesh Sharma , Buck Gremel , Ian Steiner
IPC: G06F1/3234 , G06F1/20
Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
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公开(公告)号：US09075614B2
公开(公告)日：2015-07-07
申请号：US13782492
申请日：2013-03-01
Applicant: Intel Corporation
Inventor： Eric Fetzer , Reid Riedlinger , Don Soltis , William Bowhill , Satish Shrimali , Krishnakanth Sistla , Efraim Rotem , Rakesh Kumar , Vivek Garg , Alon Naveh , Lokesh Sharma
CPC classification number: G06F1/3296 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
Abstract translation: 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。
