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公开(公告)号：US20220207138A1
公开(公告)日：2022-06-30
申请号：US17134350
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Alaa Alameldeen , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.
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公开(公告)号：US20220206818A1
公开(公告)日：2022-06-30
申请号：US17134334
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Alaa Alameldeen , Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.
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公开(公告)号：US20220207147A1
公开(公告)日：2022-06-30
申请号：US17134343
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Alaa Alameldeen , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.
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公开(公告)号：US10922088B2
公开(公告)日：2021-02-16
申请号：US16024733
申请日：2018-06-29
Applicant: Intel Corporation
Inventor： Fangfei Liu , Bin Xing , Michael Steiner , Mona Vij , Carlos Rozas , Francis McKeen , Meltem Ozsoy , Matthew Fernandez , Krystof Zmudzinski , Mark Shanahan
Abstract: Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.
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公开(公告)号：US11797309B2
公开(公告)日：2023-10-24
申请号：US16728722
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Carlos Rozas , Francis McKeen , Pasquale Cocchini , Meltem Ozsoy , Matthew Fernandez
CPC classification number: G06F9/3844 , G06F9/30145 , G06F9/3804 , G06F9/5011
Abstract: An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities. For example, one embodiment of a processor comprises: an instruction fetcher to fetch instructions from a cache or system memory; a branch predictor to speculate a first instruction path to be taken comprising a first sequence of instructions; a decoder to decode the first sequence of instructions; execution circuitry to execute the first sequence of instructions and process data associated with the instruction to generate results; information flow tracking circuitry and/or logic to: assign labels to all or a plurality of instructions in the first sequence of instructions, track resource usage of the plurality of instructions using the labels, merge sets of labels to remove redundancies; and responsive to detecting that the first instruction path was mis-predicted, generating one or more summaries comprising resources affected by one or more of the first sequence of instructions; and recycling labels responsive to retirement of instructions associated with the labels.
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公开(公告)号：US20220207154A1
公开(公告)日：2022-06-30
申请号：US17134333
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Richard Winterton , Mohammad Reza Haghighat , Asit Mallick , Alaa Alameldeen , Abhishek Basak , Jason W. Brandt , Michael Chynoweth , Carlos Rozas , Scott Constable , Martin Dixon , Matthew Fernandez , Fangfei Liu , Francis McKeen , Joseph Nuzman , Gilles Pokam , Thomas Unterluggauer , Xiang Zou
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.
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公开(公告)号：US20220207148A1
公开(公告)日：2022-06-30
申请号：US17134345
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Alaa Alameldeen , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.
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公开(公告)号：US20220207146A1
公开(公告)日：2022-06-30
申请号：US17134341
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Alaa Alameldeen , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.
