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    Multi-tenant cryptographic memory isolation
    1.
    发明授权
    Multi-tenant cryptographic memory isolation 有权

    公开(公告)号：US10776525B2

    公开(公告)日：2020-09-15

    申请号：US15720360

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Siddhartha Chhabra ,  Nadav Bonen

    IPC: H04L29/00 ,  G06F21/79 ,  G06F21/75 ,  G06F21/76 ,  G06F12/14 ,  G06F21/62

    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.

    Memory power management method and apparatus
    6.
    发明授权
    Memory power management method and apparatus 有权

    公开(公告)号：US12165686B2

    公开(公告)日：2024-12-10

    申请号：US17178015

    申请日：2021-02-17

    Applicant: Intel Corporation

    Inventor： Nivedha Krishnakumar ,  Virendra Vikramsinh Adsure ,  Jaya Jeyaseelan ,  Nadav Bonen ,  Barnes Cooper ,  Toby Opferman ,  Vijay Bahirji ,  Chia-Hung Kuo

    IPC: G11C11/406 ,  G11C5/14 ,  G11C11/402 ,  G11C11/4074

    Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

    ARCHITECTURE FOR DYNAMIC TRANSFORMATION OF MEMORY CONFIGURATION
    10.
    发明申请
    ARCHITECTURE FOR DYNAMIC TRANSFORMATION OF MEMORY CONFIGURATION 审中-公开

    公开(公告)号：US20190042157A1

    公开(公告)日：2019-02-07

    申请号：US16024637

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Julius Mandelblat ,  Nir Sucher

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

    Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

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