公开(公告)号：US10528473B2

公开(公告)日：2020-01-07

申请号：US15621401

申请日：2017-06-13

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0804 ,  G06F1/3234

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

公开(公告)号：US08856569B2

公开(公告)日：2014-10-07

申请号：US13784208

申请日：2013-03-04

Applicant: Intel Corporation

Inventor： Pedro Chaparro Monferrer ,  Jose Gonzalez

IPC: G06F1/20 ,  G06F1/32 ,  H01L23/34 ,  H01L23/38 ,  G05D23/19

CPC classification number: G05D23/19 ,  G06F1/32 ,  H01L23/34 ,  H01L23/38 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control.

Abstract translation: 具有多个核的装置执行一种算法来控制采用珀尔帖效应的薄膜热电冷却器（TFTEC），以从多核处理器的各种核心去除热量。 这些算法可以组合线程迁移（TM）和动态电压/频率缩放（DVFS）来提供动态热管理（DTM）和TFTEC控制。