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公开(公告)号：US11551956B2
公开(公告)日：2023-01-10
申请号：US16911466
申请日：2020-06-25
Applicant: Intel Corporation
Inventor： Chandrashekara Shashank Kaira , Phillip C. Miller , Purushotham Kaushik Muthur Srinath , Deepak Goyal
Abstract: According to the various examples, a fully integrated system and method for failure analysis using RF-based thermometry enable the detection and location of defects and failures in complex semiconductor packaging architectures. The system provides synchronous amplified RF signals to generate unique thermal signatures at defect locations based on dielectric relaxation loss and heating.
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公开(公告)号：US10607909B2
公开(公告)日：2020-03-31
申请号：US16075120
申请日：2016-04-02
Applicant: Intel Corporation
Inventor： Purushotham Kaushik Muthur Srinath , Pramod Malatkar , Sairam Agraharam , Chandra M. Jha , Arnab Choudhury , Nachiket R. Raravikar
IPC: H01L23/367 , H01L23/26 , H01L23/433 , H01L25/065 , H01L23/36 , H01L23/00 , H01L25/18 , H01L23/31
Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.
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公开(公告)号：US11476120B2
公开(公告)日：2022-10-18
申请号：US16481056
申请日：2017-03-30
Applicant: Intel Corporation
IPC: H01L21/027 , H01J37/31 , H01L21/265 , H01J37/30
Abstract: Systems and methods of sample preparation using dual ion beam trenching are described. In an example, an inside of a semiconductor package is non-destructively imaged to determine a region of interest (ROI). A mask is positioned over the semiconductor package, and a mask window is aligned with the ROI. A first ion beam and a second ion beam are swept, simultaneously or sequentially, along an edge of the mask window to trench the semiconductor package and to expose the ROI for analysis.
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公开(公告)号：US20180283845A1
公开(公告)日：2018-10-04
申请号：US15476187
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Mario Pacheco , Manish Dubey , Purushotham Kaushik Muthur Srinath , Deepak Goyal , Liwen Jin
Abstract: An interferometer for characterizing a sample, the interferometer including a light emitter to produce a light beam. A wavelength modulator can dither a wavelength of the light beam to produce an input beam having an oscillating wavelength. A beam splitter can be configured to divide the input beam into a reference beam and a measurement beam. The reference beam can reflect from a mirror having a fixed position and return to the beam splitter. The measurement beam can reflect from the sample and return to the beam splitter. The beam splitter can interfere the received reference beam and measurement beam to form an output beam. A detector can convert the output beam to an electrical signal. A processor can control the wavelength modulator, receive the electrical signal, and determine a distance to the sample based on the electrical signal and the oscillating wavelength of the input beam.
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公开(公告)号：US09625256B1
公开(公告)日：2017-04-18
申请号：US14757973
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Purushotham Kaushik Muthur Srinath , Mario Pacheco , Deepak Goyal
IPC: G01B11/27
CPC classification number: G01B11/272 , H01K3/00 , H01L24/00
Abstract: Techniques and mechanisms for evaluating misalignment of circuit structures. In an embodiment, infrared (IR) radiation is variously focused on different planes of an assembly including an integrated circuit (IC) chip and a substrate that is to be coupled to, or that is coupled to, the IC chip. The cross-sectional planes include respective structures that variously reflect IR radiation. The reflected IR radiation is measured to create images each representing a corresponding cross-section of the assembly. In another embodiment, respective reference features of the images are identified and evaluated to determine whether a misalignment between the reference features satisfies one or more threshold test conditions.
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公开(公告)号：US20180254256A1
公开(公告)日：2018-09-06
申请号：US15762837
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Pilin Liu , Purushotham Kaushik Muthur Srinath , Deepak Goyal
IPC: H01L23/00 , B23K35/26 , B23K35/02 , H01L21/768
CPC classification number: H01L24/81 , B23K35/0222 , B23K35/0233 , B23K35/0238 , B23K35/26 , B23K35/264 , H01L21/76843 , H01L23/48 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0239 , H01L2224/0401 , H01L2224/05647 , H01L2224/11462 , H01L2224/13082 , H01L2224/13083 , H01L2224/13113 , H01L2224/13147 , H01L2224/16147 , H01L2224/81447 , H01L2224/81815 , H01L2924/00014 , H01L2924/0105 , H01L2924/01322
Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).
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7.发明授权Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures 有权防止填料在微电子器件中捕获到微电子衬底互连结构的方法
公开(公告)号：US08999765B2
公开(公告)日：2015-04-07
申请号：US13925967
申请日：2013-06-25
Applicant: Intel Corporation
Inventor： Manish Dubey , Rajendra C. Dias , Yonghao Xiu , Arjun Krishnan , Yiqun Bai , Purushotham Kaushik Muthur Srinath
IPC: H01L23/488 , H01L21/56
CPC classification number: H01L21/563 , H01L23/00 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.
Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后，将微电子器件附着到具有互连结构的微电子衬底的方法，其中在将微电子器件连接到底部填充材料之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。
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公开(公告)号：US11705383B2
公开(公告)日：2023-07-18
申请号：US16550773
申请日：2019-08-26
Applicant: Intel Corporation
CPC classification number: H01L23/481 , H01L23/315
Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.
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公开(公告)号：US20210407833A1
公开(公告)日：2021-12-30
申请号：US16911466
申请日：2020-06-25
Applicant: Intel Corporation
Inventor： Chandrashekara Shashank Kaira , Phillip C. Miller , Purushotham Kaushik Muthur Srinath , Deepak Goyal
Abstract: According to the various examples, a fully integrated system and method for failure analysis using RF-based thermometry enable the detection and location of defects and failures in complex semiconductor packaging architectures. The system provides synchronous amplified RF signals to generate unique thermal signatures at defect locations based on dielectric relaxation loss and heating.
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公开(公告)号：US10361167B2
公开(公告)日：2019-07-23
申请号：US15762837
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Pilin Liu , Purushotham Kaushik Muthur Srinath , Deepak Goyal
IPC: H01L23/00 , H01L23/48 , B23K35/26 , B23K35/02 , H01L21/768
Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).
