公开(公告)号：US12183831B2

公开(公告)日：2024-12-31

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Miriam R. Reshotko ,  Shriram Shivaraman ,  Li Huey Tan ,  Tristan A. Tronic ,  Jack T. Kavalieros

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317851A1

公开(公告)日：2023-10-05

申请号：US17711887

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Pushkar Ranade ,  Willy Rachmady ,  Ravi Pillarisetty

IPC: H01L29/786 ,  H01L27/092 ,  H01L23/473 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L27/092 ,  H01L23/473 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/8258 ,  H01L29/66522 ,  H01L29/66742

Abstract: Integrated circuit (IC) including transistors with high-mobility/high-saturation velocity, non-silicon channel materials coupled to a silicon substrate through counter-doped sub-channel materials, which greatly reduce electrical leakage currents through the substrate when the IC is operated at very low temperatures (e.g., below −25 C). With low temperature operation, high transistor performance associated with the non-silicon channel materials can be integrated into high density IC architectures that avoid the limitations associated with semiconductor material layer transfers.

公开(公告)号：US20230275087A1

公开(公告)日：2023-08-31

申请号：US18311582

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L27/088 ,  G06N10/00 ,  H10N69/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/088 ,  G06N10/00 ,  H01L21/823456 ,  H01L29/66977 ,  H01L29/778 ,  H10N69/00 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US11735595B2

公开(公告)日：2023-08-22

申请号：US17721236

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Abhishek A. Sharma ,  Elijah V. Karpov

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L29/42384 ,  H01L29/785

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

公开(公告)号：US11721724B2

公开(公告)日：2023-08-08

申请号：US17364985

申请日：2021-07-01

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/82

CPC classification number: H01L29/122 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66977 ,  H01L29/66984 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US11700776B2

公开(公告)日：2023-07-11

申请号：US17592724

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Van H. Le

IPC: H10N60/10 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80 ,  H10N60/01

CPC classification number: H10N60/128 ,  G06N10/00 ,  H10N60/0912 ,  H10N60/12 ,  H10N60/805

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

公开(公告)号：US11616126B2

公开(公告)日：2023-03-28

申请号：US16143641

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/66 ,  B82Y10/00 ,  G06N10/00 ,  H01L29/76 ,  H01L29/06 ,  H01L29/778 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165 ,  H01L29/82 ,  H01L21/8234 ,  H01L29/16

Abstract: A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.

公开(公告)号：US11575035B2

公开(公告)日：2023-02-07

申请号：US17481406

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  James S. Clarke ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/12 ,  H01L29/423 ,  H01L29/76

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.

公开(公告)号：US11569243B2

公开(公告)日：2023-01-31

申请号：US16140890

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Willy Rachmady ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L27/108 ,  H01L23/48

Abstract: A DRAM integrated circuit device is described in which at least some of the peripheral circuits associated with the memory arrays are provided on a first substrate. The memory arrays are provided on a second substrate stacked on the first substrate, thus forming a DRAM integrated circuit device on a stacked-substrate assembly. Vias that electrically connect the memory arrays on the second substrate to the peripheral circuits on the first substrate are fabricated using high aspect ratio via fabrication techniques.

公开(公告)号：US11522011B2

公开(公告)日：2022-12-06

申请号：US16631156

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov ,  Brian S. Doyle ,  Abhishek A. Sharma

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.