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公开(公告)号：US20250006646A1
公开(公告)日：2025-01-02
申请号：US18216525
申请日：2023-06-29
Applicant: Intel Corporation
Inventor： Xing Sun , Srinivas Pietambaram , Darko Grujicic , Rengarajan Shanmugam , Brian Balch , Micah Armstrong , Qiang Li , Marcel Wall , Rahul Manepalli
IPC: H01L23/538 , H01L21/48 , H01L23/00 , H01L23/15 , H01L25/065
Abstract: Integrated circuit (IC) die packages including a glass with conductive through-glass vias (TGVs). The TGVs are lined with a buffer comprising an inorganic material having a low elastic (Young's) modulus. The buffer may thereby accommodate internal stress between the glass and through via metallization formed over the buffer. The compliant inorganic material may be a metal or metal alloy, for example, different than that of the via metallization. The inorganic material may also be a metal nitride, metal silicide, or metal carbide. A TGV buffer may be one material layer of a stack comprising two or more material layers deposited upon TGV sidewall surfaces. A routing structure may be built-up on at least one side of the glass and IC die assembled to the routing structure. The buffer Ipresent within the TGVs may be absent from metal features of the routing structure.
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公开(公告)号：US20240321657A1
公开(公告)日：2024-09-26
申请号：US18189782
申请日：2023-03-24
Applicant: Intel Corporation
Inventor： Darko Grujicic , Suddhasattwa Nad , Srinivas Pietambaram , Rengarajan Shanmugam , Marcel Wall , Sashi Kandanur , Rahul Manepalli , Robert May
IPC: H01L23/15 , H01L23/498
CPC classification number: H01L23/15 , H01L23/49827 , H01L23/49866 , G02B6/4214
Abstract: Photonic integrated circuit packages and methods of manufacturing are disclosed. An example integrated circuit package includes: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate including a glass core, the glass core including a through glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through glass via, the recess defined by a third surface of the glass core, the recess having a different shape than the through glass via; and a reflective metal disposed on the third surface to define a mirror, the reflective metal also disposed between a wall of the through glass via and a conductive material disposed in the through glass via.
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公开(公告)号：US20240006258A1
公开(公告)日：2024-01-04
申请号：US17856969
申请日：2022-07-02
Applicant: Intel Corporation
Inventor： Suddhasattwa Nad , Darko Grujicic , Rengarajan Shanmugam
IPC: H01L23/15 , H01L23/498 , H01L21/48
CPC classification number: H01L23/15 , H01L23/49866 , H01L23/49833 , H01L23/49822 , H01L21/4857 , H01L21/486 , H01L23/49816 , H01L24/16
Abstract: Substrates with nitrided glass cores, and methods of forming the same, are described herein. In one example, a substrate includes one or more glass layers and a plurality of dielectric layers. At least one of the glass layers includes nitrogen. Further, at least one of the dielectric layers is above the one or more glass layers and at least one of the dielectric layers is below the one or more glass layers.
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公开(公告)号：US20230420358A1
公开(公告)日：2023-12-28
申请号：US17851957
申请日：2022-06-28
Applicant: Intel Corporation
Inventor： Cemil S. Geyik , Kristof Kuwawi Darmawikarta , Zhiguo Qian , Kemal Aygun , Jung Kyu Han , Srinivas V. Pietambaram , Rengarajan Shanmugam , Robert L. Sankman
IPC: H01L23/498 , H01L23/538 , H01L21/48
CPC classification number: H01L23/49894 , H01L23/49822 , H01L23/5383 , H01L21/4857
Abstract: Disclosed herein are silver-coated conductive structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a first material layer on a top surface and on side surfaces of the conductive line, the first material layer including silver, and a second material layer on the first material layer, the second material layer including silicon or aluminum, and one or more of nitrogen and oxygen.
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公开(公告)号：US12159844B2
公开(公告)日：2024-12-03
申请号：US17029866
申请日：2020-09-23
Applicant: Intel Corporation
Inventor： Benjamin Duong , Roy Dittler , Darko Grujicic , Chandrasekharan Nair , Rengarajan Shanmugam
Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.
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公开(公告)号：US11728265B2
公开(公告)日：2023-08-15
申请号：US16129711
申请日：2018-09-12
Applicant: Intel Corporation
Inventor： Brandon C. Marin , Frank Truong , Shivasubramanian Balasubramanian , Dilan Seneviratne , Yonggang Li , Sameer Paital , Darko Grujicic , Rengarajan Shanmugam , Melissa Wette , Srinivas Pietambaram
IPC: H01L23/498 , H01L21/48 , H01L23/522 , H01L49/02 , H01L21/768 , H01L23/00 , H01L27/01 , H01L23/64
CPC classification number: H01L23/5228 , H01L21/4846 , H01L21/76871 , H01L23/498 , H01L23/5226 , H01L23/647 , H01L24/09 , H01L27/016 , H01L28/24
Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
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公开(公告)号：US11291122B2
公开(公告)日：2022-03-29
申请号：US16637545
申请日：2017-09-22
Applicant: Intel Corporation
Inventor： Darko Grujicic , Rengarajan Shanmugam , Sandeep Gaan , Adrian Bayraktaroglu , Roy Dittler , Ke Liu , Suddhasattwa Nad , Marcel A. Wall , Rahul N. Manepalli , Ravindra V. Tanikella
IPC: C23C18/38 , H05K3/38 , C23C18/16 , C23C18/18 , H01L21/48 , H05K3/42 , H05K3/46 , H05K1/11 , H01L23/14
Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.
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公开(公告)号：US20230095846A1
公开(公告)日：2023-03-30
申请号：US17485039
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Benjamin T. Duong , Srinivas V. Pietambaram , Aleksandar Aleksov , Helme Castro De La Torre , Kristof Darmawikarta , Darko Grujicic , Sashi S. Kandanur , Suddhasattwa Nad , Rengarajan Shanmugam , Thomas I. Sounart , Marcel A. Wall
IPC: H01L23/498 , H01G4/33 , H01L21/48
Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.
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公开(公告)号：US11574993B2
公开(公告)日：2023-02-07
申请号：US16271639
申请日：2019-02-08
Applicant: Intel Corporation
Inventor： Rengarajan Shanmugam , Suddhasattwa Nad , Darko Grujicic , Srinivas Pietambaram
IPC: H01L23/498 , H01F27/28 , H01L21/48 , H01L49/02 , H01L23/66 , H01F27/24 , H01L25/16 , H01L23/552 , H01F41/04 , H01L23/00
Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.
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公开(公告)号：US20220093535A1
公开(公告)日：2022-03-24
申请号：US17029866
申请日：2020-09-23
Applicant: Intel Corporation
Inventor： Benjamin Duong , Roy Dittler , Darko Grujicic , Chandrasekharan Nair , Rengarajan Shanmugam
Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.
