公开(公告)号：US11100023B2

公开(公告)日：2021-08-24

申请号：US15718178

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ruirui Huang ,  Nilanjan Palit ,  Robert P. Adler ,  Ioannis T. Schoinas ,  Avishay Snir ,  Boris Dolgunov

IPC: G06F13/40 ,  H04L12/741 ,  G06F15/78 ,  H04L29/06

Abstract: In one example, a semiconductor die includes a plurality of agents and a fabric coupled to at least some of the plurality of agents. The fabric may include at least one router to provide communication between two or more of the plurality of agents, the at least one router coupled to a first agent of the plurality of agents, where the first agent is to send a first message to the at least one router, the first message comprising a first header including a first source identifier, and the at least one router is to validate that the first source identifier is associated with the first agent and if so to direct the first message towards a destination agent, and otherwise to prevent the first message from being directed towards the destination agent. Other embodiments are described and claimed.

公开(公告)号：US10235486B2

公开(公告)日：2019-03-19

申请号：US15279725

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Krishnan Srinivasan ,  Robert P. Adler ,  Robert De Gruijl ,  Jay Tomlinson ,  Eric A. Geisler

IPC: G06F17/50

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.

公开(公告)号：US20190033368A1

公开(公告)日：2019-01-31

申请号：US15801454

申请日：2017-11-02

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Robert P. Adler ,  Ki Yoon

IPC: G01R31/3187

Abstract: In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.

公开(公告)号：US10164880B2

公开(公告)日：2018-12-25

申请号：US14541472

申请日：2014-11-14

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Rohit R. Verma ,  Robert P. Adler

IPC: H04L12/741 ,  H04L29/06 ,  G06F15/78 ,  G06F13/40

Abstract: In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.

公开(公告)号：US09727679B2

公开(公告)日：2017-08-08

申请号：US14578418

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Robert P. Adler

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F9/4403 ,  G06F9/4411 ,  G06F13/42 ,  G06F13/4221

Abstract: A topology metadata file is identified that describes a topology of a system on chip (SoC) to be created, where the topology includes a plurality of computing blocks to be interconnected by a fabric. A corresponding computing block metadata file is identified for each of the plurality of computing blocks, where each of the computing block metadata files is to describe attributes of the corresponding computing block. The topology metadata file and the computing block metadata files are parsed to identify configuration attributes of the SoC. An intermediate representation of the SoC is generated based on the configuration attributes.

公开(公告)号：US11372674B2

公开(公告)日：2022-06-28

申请号：US17080970

申请日：2020-10-27

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Robert De Gruijl ,  Sridhar Lakshmanamurthy ,  Ramadass Nagarajan ,  Peter J. Elardo

IPC: G06F9/46 ,  G06F13/42 ,  G06F15/78 ,  G06F15/76

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US20190340313A1

公开(公告)日：2019-11-07

申请号：US16509482

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Husnara Khan ,  Satish Venkatesan ,  Ramamurthy Sunder ,  Mukesh K. Mishra ,  Bindu Lalitha ,  Hassan M. Shehab ,  Sandhya Seshadri ,  Dhrubajyoti Kalita ,  Wendy Liu ,  Hanumanth Bollineni ,  Snehal Kharkar

IPC: G06F17/50

Abstract: Methods and apparatus relating to subsystem-based System on Chip (SoC) integration are described. In one embodiment, logic circuitry determines one or more components of a subsystem. The subsystem supports an architectural feature to be implemented on a System on Chip (SoC) device. A first interface communicatively couples a first component of the subsystem to a first component of another subsystem. A second interface communicatively couples at least one component of the subsystem to at least one chassis component of the SoC device or communicatively couples the at least one component of the subsystem to at least one non-chassis component of the other subsystem. In an embodiment, components of the subsystem may be packaged such that the packaging generates a reusable collateral that allows for fast integration of all aspects of design in any SoC device with a compatible chassis prior to manufacture.

公开(公告)号：US09891282B2

公开(公告)日：2018-02-13

申请号：US14998200

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Robert P. Adler ,  Suketu U. Bhatt ,  Robert De Gruijl ,  Kah Meng Yeem

IPC: G01R31/28 ,  G01R31/3177 ,  H03K19/177 ,  H03K19/21

CPC classification number: G01R31/3177 ,  H03K19/17704 ,  H03K19/21

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

公开(公告)号：US20160182186A1

公开(公告)日：2016-06-23

申请号：US14578313

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Geetani R. Edirisooriya ,  Joseph Murray ,  Deep K. Buch

IPC: H04L1/00

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract translation: 提供入站边带接口以通过第一边带链路接收消息，并且提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶位线。 消息通过至少一些数据线转发，并且奇偶校验位通过奇偶校验位线发送到另一设备以对应于消息。

公开(公告)号：US09064051B2

公开(公告)日：2015-06-23

申请号：US14295810

申请日：2014-06-04

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/366 ,  G06F15/78 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求 源代理程序在第一个时钟周期。 然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。 描述和要求保护其他实施例。