公开(公告)号：US20230342234A1

公开(公告)日：2023-10-26

申请号：US17724811

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Santhosh Raghuram Krishnaswamy ,  Siddhartha Selvaraj ,  Anshul Soni ,  Toby Zimmerman

IPC: G06F11/07 ,  G06F9/4401

CPC classification number: G06F11/0766 ,  G06F9/4406 ,  G06F11/0721

Abstract: The technology describe herein includes upon entering a mode of a processor that is not visible to an operating system (OS), setting a flag indicating entry into the mode and saving an identifier (ID) of an error causing entry into the mode; and responsive to a system reset initiation while in the mode, booting a basic input/output system (BIOS), creating an error record to be accessible to the OS after booting, the error record including the flag and the error ID, and booting the OS.

公开(公告)号：US20220011842A1

公开(公告)日：2022-01-13

申请号：US17484335

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Nagabhushan Reddy ,  Abhinay Gupta ,  Vinithra Janarthanan ,  Santhosh Raghuram Krishnaswamy ,  Pannerkumar Rajagopal ,  Siddharth Selvaraj ,  Mihir Shah ,  Vishwanath Somayaji

IPC: G06F1/30 ,  G06F1/3225 ,  G06F11/07

Abstract: An apparatus comprises a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, store state information in a volatile memory of the computer device, and start a timer for a time-out period for performing the first process. First components of the computer device are in a low power state. A second circuitry to detect, after the time-out period, a failure of the first process. A third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device. The volatile memory is operational in the first operating mode and is in a low power state in the second operating mode.