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公开(公告)号:US20240114622A1
公开(公告)日:2024-04-04
申请号:US17956338
申请日:2022-09-29
Applicant: Intel Corporation
Inventor: Kristof Darmawikarta , Srinivas Venkata Ramanuja Pietambaram , Tarek A. Ibrahim , Cary Kuliasha , Siddharth K. Alur , Jung Kyu Han , Beomseok Choi , Russell K. Mortensen , Andrew Collins , Haobo Chen , Brandon C. Marin
IPC: H05K1/18 , H01L23/498 , H01L23/538 , H01L23/64 , H01L25/065 , H05K3/00 , H05K3/46
CPC classification number: H05K1/185 , H01L23/49822 , H01L23/5389 , H01L23/645 , H01L25/0655 , H05K3/0047 , H05K3/4644 , H05K2201/1003 , H05K2201/10674
Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.
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公开(公告)号:US11935805B2
公开(公告)日:2024-03-19
申请号:US18133868
申请日:2023-04-12
Applicant: Intel Corporation
Inventor: Rahul Jain , Kyu Oh Lee , Siddharth K. Alur , Wei-Lun K. Jen , Vipul V. Mehta , Ashish Dhall , Sri Chaitra J. Chavali , Rahul N. Manepalli , Amruthavalli P. Alur , Sai Vadlamani
IPC: H01L23/31 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/498 , H01L23/532 , H01L23/538 , H01L25/065
CPC classification number: H01L23/3185 , H01L21/4853 , H01L21/4857 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L23/53295 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2224/16227 , H01L2224/81 , H01L2224/83051 , H01L2924/18161
Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20230223278A1
公开(公告)日:2023-07-13
申请号:US18118835
申请日:2023-03-08
Applicant: Intel Corporation
Inventor: Sri Chaitra Jyotsna Chavali , Siddharth K. Alur , Lilia May , Amanda E. Shuckman
IPC: H01L21/48 , H01L23/498
CPC classification number: H01L21/4857 , H01L23/49822 , H01L23/49827
Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
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公开(公告)号:US11158558B2
公开(公告)日:2021-10-26
申请号:US16464547
申请日:2016-12-29
Applicant: INTEL CORPORATION
Inventor: Rahul Jain , Kyu Oh Lee , Siddharth K. Alur , Wei-Lun K. Jen , Vipul V. Mehta , Ashish Dhall , Sri Chaitra J. Chavali , Rahul N. Manepalli , Amruthavalli P. Alur , Sai Vadlamani
IPC: H01L23/48 , H01L21/00 , H01L21/44 , H05K7/00 , H01R9/00 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/538 , H01L23/00 , H01L25/065 , H01L23/532 , H01L23/498
Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20190326222A1
公开(公告)日:2019-10-24
申请号:US16473599
申请日:2017-03-30
Applicant: INTEL CORPORATION
Inventor: Sri Chaitra J. Chavali , Liwei Cheng , Siddharth K. Alur , Sheng Li
IPC: H01L23/538 , H01L21/48 , H01L23/498 , H01L21/027 , H01L25/18
Abstract: An apparatus system is provided which comprises: a substrate; a metal pillar formed on the substrate, the metal pillar comprising a first section and a second section, wherein the first section of the metal pillar is formed by depositing metal in a first opening of a first photoresist layer, and wherein the second section of the metal pillar is formed by depositing metal in a second opening of a second photoresist layer.
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公开(公告)号:US12224253B2
公开(公告)日:2025-02-11
申请号:US17480064
申请日:2021-09-20
Applicant: Intel Corporation
Inventor: Xin Ning , Brandon C. Marin , Kyu Oh Lee , Siddharth K. Alur , Numair Ahmed , Brent Williams , Mollie Stewart , Nathan Ou , Cary Kuliasha
IPC: H01L23/64 , H01F27/28 , H01L21/48 , H01L23/498 , H01L49/02
Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.
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公开(公告)号:US11664290B2
公开(公告)日:2023-05-30
申请号:US17459993
申请日:2021-08-27
Applicant: INTEL CORPORATION
Inventor: Rahul Jain , Kyu Oh Lee , Siddharth K. Alur , Wei-Lun K. Jen , Vipul V. Mehta , Ashish Dhall , Sri Chaitra J. Chavali , Rahul N. Manepalli , Amruthavalli P. Alur , Sai Vadlamani
IPC: H01L23/31 , H01L21/48 , H01L21/56 , H01L23/498 , H01L23/532 , H01L23/538 , H01L23/00 , H01L25/065
CPC classification number: H01L23/3185 , H01L21/4853 , H01L21/4857 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/53295 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2224/16227 , H01L2224/81 , H01L2224/83051 , H01L2924/18161
Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
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公开(公告)号:US11631595B2
公开(公告)日:2023-04-18
申请号:US17521406
申请日:2021-11-08
Applicant: Intel Corporation
Inventor: Sri Chaitra Jyotsna Chavali , Siddharth K. Alur , Lilia May , Amanda E. Schuckman
IPC: H01L21/48 , H01L23/498
Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
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公开(公告)号:US10727184B2
公开(公告)日:2020-07-28
申请号:US16145683
申请日:2018-09-28
Applicant: Intel Corporation
Inventor: Siddharth K. Alur , Srinivas V. Pietambaram
IPC: H01L23/532 , H01L21/768 , H01L23/522 , H01L23/498 , H01L25/065 , H01L21/02 , H01L23/00
Abstract: Described are example microelectronic devices including structures, such as build-up layers, formed of a non-homogeneous photoimageable dielectric material. The non-homogeneous photoimageable dielectric material includes two regions forming opposite surfaces of the material. A first region includes a first carbon content, and a second region located above the first region includes a second carbon content which is greater than that of the first region. The second region of the photoimageable dielectric material provides enhanced adhesion with metal that may be deposited above the material, such as a sputtered metal seed layer to facilitate subsequent deposition of an electroless metal over the non-homogeneous photoimageable dielectric material.
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公开(公告)号:US20180281374A1
公开(公告)日:2018-10-04
申请号:US15475157
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Ji Yong Park , Sri Chaitra J. Chavali , Siddharth K. Alur , Kyu Oh Lee
CPC classification number: B32B37/10 , B32B37/06 , B32B2307/202 , B32B2309/02 , B32B2457/08 , H05K3/0064 , H05K3/022 , H05K3/4602 , H05K2203/0278 , H05K2203/068
Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.
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