公开(公告)号：US09195600B2

公开(公告)日：2015-11-24

申请号：US14536805

申请日：2014-11-10

Applicant: Intel Corporation

Inventor： Ali-Reza Adl-Tabatabai ,  Yang Ni ,  Bratin Saha ,  Vadim Bassin ,  Gad Sheaffer ,  David Callahan ,  Jan Gray

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F12/10 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器 在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。 描述和要求保护其他实施例。

公开(公告)号：US08886894B2

公开(公告)日：2014-11-11

申请号：US13658264

申请日：2012-10-23

Applicant: Intel Corporation

Inventor： Ali-Reza Adl-Tabatabai ,  Yang Ni ,  Bratin Saha ,  Vadim Bassin ,  Gad Sheaffer ,  David Callahan ,  Jan Gray

IPC: G06F12/16

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

公开(公告)号：US20230018828A1

公开(公告)日：2023-01-19

申请号：US17374728

申请日：2021-07-13

Applicant: Intel Corporation

Inventor： Vadim Bassin ,  Eliezer Weissmann ,  Efraim Rotem ,  Julius Mandelblat

IPC: G06F1/3293 ,  G06F1/3228 ,  G06F9/48

Abstract: Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.

公开(公告)号：US08856466B2

公开(公告)日：2014-10-07

申请号：US13658360

申请日：2012-10-23

Applicant: Intel Corporation

Inventor： Ali-Reza Adl-Tabatabai ,  Yang Ni ,  Bratin Saha ,  Vadim Bassin ,  Gad Sheaffer ,  David Callahan ,  Jan Gray

IPC: G06F12/16

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器 在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。 描述和要求保护其他实施例。