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    Remote atomic operations in multi-socket systems
    4.
    发明授权
    Remote atomic operations in multi-socket systems 有权

    公开(公告)号：US11537520B2

    公开(公告)日：2022-12-27

    申请号：US17494651

    申请日：2021-10-05

    Applicant: Intel Corporation

    Inventor： Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  Christopher J. Hughes ,  Jonas Svennebring ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  David A. Koufaty

    IPC: G06F12/0815 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0817 ,  G06F12/0831

    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

    REMOTE ATOMIC OPERATIONS IN MULTI-SOCKET SYSTEMS
    6.
    发明申请
    REMOTE ATOMIC OPERATIONS IN MULTI-SOCKET SYSTEMS 有权

    公开(公告)号：US20220091983A1

    公开(公告)日：2022-03-24

    申请号：US17494651

    申请日：2021-10-05

    Applicant: Intel Corporation

    Inventor： Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  Christopher J. Hughes ,  Jonas Svennebring ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  David A. Koufaty

    IPC: G06F12/0815 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0817

    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

    SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS
    7.
    发明申请
    SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS 审中-公开

    公开(公告)号：US20200319886A1

    公开(公告)日：2020-10-08

    申请号：US16799619

    申请日：2020-02-24

    Applicant: Intel Corporation

    Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

    IPC: G06F9/30 ,  G06F12/0875

    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

    Two level memory full line writes
    10.
    发明授权
    Two level memory full line writes 有权

    公开(公告)号：US10140213B2

    公开(公告)日：2018-11-27

    申请号：US15447767

    申请日：2017-03-02

    Applicant: Intel Corporation

    Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

    IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126

    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

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