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    Dynamic built-in self-test system
    2.
    发明授权
    Dynamic built-in self-test system 有权
    动态内置自检系统

    公开(公告)号：US08898530B1

    公开(公告)日：2014-11-25

    申请号：US14060872

    申请日：2013-10-23

    Applicant: International Business Machines Corporation

    Inventor： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC: G01R31/28 ,  G06F11/27

    CPC classification number: G06F11/27 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

    Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.

    Abstract translation: 一种执行动态内置自检（BIST）的方法。 该方法包括对半导体芯片上的电路进行第一次测试。 第一个测试包括第一个开关因素。 第一次测试期间的电路用一个或多个传感器进行监控。 确定监测电路的一个或多个传感器的第一传感器值。 还确定第一传感器值是否在可编程常数的范围内。 响应于确定第一传感器值在可编程常数的范围之外来确定第二开关因数。

    SELF EVALUATION OF SYSTEM ON A CHIP WITH MULTIPLE CORES
    3.
    发明申请
    SELF EVALUATION OF SYSTEM ON A CHIP WITH MULTIPLE CORES 有权

    公开(公告)号：US20140157073A1

    公开(公告)日：2014-06-05

    申请号：US13707365

    申请日：2012-12-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC: G01R31/3177

    CPC classification number: G01R31/31703 ,  G01R31/31718 ,  G01R31/3177

    Abstract: A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.

    SELF EVALUATION OF SYSTEM ON A CHIP WITH MULTIPLE CORES
    4.
    发明申请
    SELF EVALUATION OF SYSTEM ON A CHIP WITH MULTIPLE CORES 有权
    自动评估多芯片芯片系统

    公开(公告)号：US20140157072A1

    公开(公告)日：2014-06-05

    申请号：US13705353

    申请日：2012-12-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC: G01R31/317

    CPC classification number: G01R31/31703 ,  G01R31/31718 ,  G01R31/3177

    Abstract: A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.

    Abstract translation: 一种方法和结构测试芯片上的系统（SoC）或具有多个芯的其他集成电路用于芯片表征以产生部分良好状态。 每个核心上的自我评估引擎（SEE）为核心创建质量度量或部分良好的价值。 SEE执行一个或多个测试以创建核心的表征签名。 然后，SEE将核心的表征特征与相邻核心的表征签名进行比较，以确定核心的部分良好值。 SEE可以输出结果以创建详细诊断的完整特征图或部分良好图，所有核心的值都可以为整个SoC产生部分良好状态。

    Implementing enhanced scan chain diagnostics via bypass multiplexing structure
    8.
    发明授权
    Implementing enhanced scan chain diagnostics via bypass multiplexing structure 有权
    通过旁路复用结构实现增强的扫描链诊断

    公开(公告)号：US09429622B2

    公开(公告)日：2016-08-30

    申请号：US14697032

    申请日：2015-04-27

    Applicant: International Business Machines Corporation

    Inventor： Steven M. Douskey ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC: G01R31/28 ,  G01R31/3177

    CPC classification number: G01R31/318563 ,  G01R31/318558

    Abstract: A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

    Abstract translation: 一种通过旁路复用结构实现增强型扫描链诊断的方法和系统。 全扫描链结构被划分成多个单独的链，例如三个单独的分隔链，具有用于实现增强的扫描链诊断的旁路多路复用器。 每个单独的分隔链包括具有独立控制的旁路多路复用器，使得扫描数据可以通过多个不同的独立扫描路径路由，潜在地绕过故障锁存器。 从全扫描和分区扫描的组合获取的信息用于扫描故障隔离，以便能够在扫描链中进行针对零点（SA0）和卡死（SA1）故障的精确识别。

    IMPLEMENTING ENHANCED SCAN CHAIN DIAGNOSTICS VIA BYPASS MULTIPLEXING STRUCTURE
    9.
    发明申请
    IMPLEMENTING ENHANCED SCAN CHAIN DIAGNOSTICS VIA BYPASS MULTIPLEXING STRUCTURE 有权
    通过旁路多重结构实现增强扫描链诊断

    公开(公告)号：US20160216323A1

    公开(公告)日：2016-07-28

    申请号：US14606145

    申请日：2015-01-27

    Applicant: International Business Machines Corporation

    Inventor： Steven M. Douskey ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC: G01R31/3177

    CPC classification number: G01R31/318563 ,  G01R31/318558

    Abstract: A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

    Abstract translation: 一种通过旁路复用结构实现增强型扫描链诊断的方法和系统。 全扫描链结构被划分成多个单独的链，例如三个单独的分隔链，具有用于实现增强的扫描链诊断的旁路多路复用器。 每个单独的分隔链包括具有独立控制的旁路多路复用器，使得扫描数据可以通过多个不同的独立扫描路径路由，潜在地绕过故障锁存器。 从全扫描和分区扫描的组合获取的信息用于扫描故障隔离，以便能够在扫描链中进行针对零点（SA0）和卡死（SA1）故障的精确识别。

    INSERTING BYPASS STRUCTURES AT TAP POINTS TO REDUCE LATCH DEPENDENCY DURING SCAN TESTING
    10.
    发明申请
    INSERTING BYPASS STRUCTURES AT TAP POINTS TO REDUCE LATCH DEPENDENCY DURING SCAN TESTING 有权
    在扫描测试期间插入边缘点的旁路结构以减少锁定依赖

    公开(公告)号：US20160169972A1

    公开(公告)日：2016-06-16

    申请号：US14574613

    申请日：2014-12-18

    Applicant: International Business Machines Corporation

    Inventor： Steven M. Douskey ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/3172 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318594

    Abstract: A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.

    Abstract translation: 提供了一种通过识别集成电路的第一和第二组件来测试集成电路的方法和装置。 第一和第二组件可以共享使得第一和第二组件响应于集成电路的输入而产生匹配的二进制输出的关系。 可以在集成电路内选择分接点。 分接点可以位于集成电路中的旁路结构的插入将影响关系的点处。 旁路结构可以插入到抽头点处，并且旁路结构可以用于进行集成电路的测试。

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