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公开(公告)号：US11569438B2
公开(公告)日：2023-01-31
申请号：US16826796
申请日：2020-03-23
摘要： A method of manufacturing a magnetic tunnel junction device is provided. The method includes forming an MTJ stack including a reference layer, a tunnel barrier layer formed on the reference layer, a free layer formed on the barrier layer, and a cap layer formed on the free layer. The method also includes performing ion beam etching (IBE) through each layer of the MTJ stack to form at least one MTJ pillar. The method also includes forming an isolation layer on sidewalls of at least the tunnel barrier layer, the isolation layer comprising a same material as that of the tunnel barrier layer. A combined width of the isolation layer and the tunnel barrier layer is equal to or greater than a width of at least one of the reference layer and the free layer.
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公开(公告)号：US11479845B2
公开(公告)日：2022-10-25
申请号：US16591964
申请日：2019-10-03
IPC分类号： C23C8/32 , H01F3/02 , H01F3/04 , H01F17/00 , H01F27/24 , H01F41/04 , C23C14/06 , C23C16/06 , C23C14/14 , C23C16/40 , C23C14/10 , C23C16/34 , C23C28/00
摘要： Embodiments are directed to a method of forming a magnetic stack arrangement of a laminated magnetic inductor having a high frequency peak quality factor (Q). A first magnetic stack is formed having one or more magnetic layers alternating with one or more insulating layers in a first inner region of a laminated magnetic inductor. A second magnetic stack is formed opposite a surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The insulating layers are formed such that a thickness of an insulating layer in the second magnetic stack is greater than a thickness of an insulating layer in the first magnetic stack.
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公开(公告)号：US11367569B2
公开(公告)日：2022-06-21
申请号：US16107102
申请日：2018-08-21
IPC分类号： H01F41/02 , H01F17/00 , H01F27/245
摘要： Embodiments of the invention are directed to a method of fabricating a yoke arrangement of an inductor. A non-limiting example method includes forming a dielectric layer across from a major surface of a substrate. The method further includes configuring the dielectric layer such that it imparts a predetermined dielectric layer compressive stress on the substrate. A magnetic stack is formed on an opposite side of the dielectric layer from the substrate, wherein the magnetic stack includes one or more magnetic layers alternating with one or more insulating layers. The method further includes configuring the magnetic stack such that it imparts a predetermined magnetic stack tensile stress on the dielectric layer, wherein a net effect of the predetermined dielectric layer compressive stress and the predetermined magnetic stack tensile stress on the substrate is insufficient to cause a portion of the major surface of the substrate to be substantially non-planar.
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公开(公告)号：US11311234B2
公开(公告)日：2022-04-26
申请号：US15808137
申请日：2017-11-09
发明人： Hariklia Deligianni , Bruce B. Doris , Steven J. Holmes , Emily R. Kinser , Qinghuang Lin , Roy R. Yu
摘要： A sensing and treatment device includes an array of metal nanorod electrodes formed on a substrate, the array including first electrodes for sensing, and second electrodes for electrical pulsation. A data processing system is configured to monitor a parameter using the first electrodes and to activate the electrical pulsation in the second electrodes in accordance with a reading of the parameter.
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公开(公告)号：US11241174B2
公开(公告)日：2022-02-08
申请号：US15175220
申请日：2016-06-07
发明人： Bruce B. Doris , Sufi Zafar
IPC分类号： A61B5/05 , A61B5/145 , A61B5/1477 , A61B5/00
摘要： A wearable monitoring system includes a first flexible substrate encapsulating a current ramping system to provide a current to an electrode in direct contact with a predetermined location of skin of a user to promote bodily fluid secretion, and a second flexible substrate placed over the predetermined location, the second flexible substrate having an integrated electrochemical sensor to determine bodily fluid concentration levels secreted through the skin.
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6.发明授权公开(公告)号：US11170933B2
公开(公告)日：2021-11-09
申请号：US16391383
申请日：2019-04-23
IPC分类号： H01F41/02 , H01F17/00 , H01F27/245
摘要： Embodiments of the invention are directed to a method of fabricating a yoke arrangement of an inductor. A non-limiting example method includes forming a dielectric layer across from a major surface of a substrate. The method further includes configuring the dielectric layer such that it imparts a predetermined dielectric layer compressive stress on the substrate. A magnetic stack is formed on an opposite side of the dielectric layer from the substrate, wherein the magnetic stack includes one or more magnetic layers alternating with one or more insulating layers. The method further includes configuring the magnetic stack such that it imparts a predetermined magnetic stack tensile stress on the dielectric layer, wherein a net effect of the predetermined dielectric layer compressive stress and the predetermined magnetic stack tensile stress on the substrate is insufficient to cause a portion of the major surface of the substrate to be substantially non-planar.
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公开(公告)号：US20210336046A1
公开(公告)日：2021-10-28
申请号：US16855777
申请日：2020-04-22
发明人： Junli Wang , Alexander Reznicek , Ruilong Xie , Bruce B. Doris
摘要： A method of forming a vertical transport fin field effect transistor device is provided. The method includes replacing a portion of a sacrificial exclusion layer between one or more vertical fins and a substrate with a temporary inner spacer. The method further includes removing a portion of a fin layer and the sacrificial exclusion layer between the one or more vertical fins and the substrate, and forming a bottom source/drain on the temporary inner spacer and between the one or more vertical fins and the substrate. The method further includes replacing a portion of the bottom source/drain with a temporary gap filler, and replacing the temporary gap filler and temporary inner spacer with a wrap-around source/drain contact having an L-shaped cross-section.
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公开(公告)号：US11152890B2
公开(公告)日：2021-10-19
申请号：US16800348
申请日：2020-02-25
发明人： Sudipto Chakraborty , Rajiv Joshi , Bruce B. Doris
摘要： A voltage controlled oscillator (VCO) circuit employing digital amplitude control of the output oscillating signal and method of operation. The digital control is provided by an analog to digital converter (ADC) element that is shared among many other operating blocks in a system. In a configuration, the oscillator current is obtained by implementing transistors in a linear region and controlling them digitally. The optimum amplitude detection is performed by measuring the DC voltage at the common mode nodes in the oscillator, and is realized using reduced time compared to an extensive frequency measurement over a long time window. The digital control is implemented using an on-chip regulator, and employs digital controls for adjusting the current consumption which leads to low on-chip area overhead, low cost, and a scalable implementation. In an implementation, a one-time code can be obtained for optimum phase noise operation when providing the digital amplitude control.
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公开(公告)号：US11152563B2
公开(公告)日：2021-10-19
申请号：US16555527
申请日：2019-08-29
摘要： A dielectric material structure is formed laterally adjacent to a bottom portion of a bottom electrode metal-containing portion that extends upward from an electrically conductive structure that is embedded in an interconnect dielectric material layer. The physically exposed top portion of the bottom electrode metal-containing portion is then trimmed to provide a bottom electrode of unitary construction (i.e., a single piece) that has a lower portion having a first diameter and an upper portion that has a second diameter that is greater than the first diameter. The presence of the dielectric material structure prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.
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公开(公告)号：US20210313252A1
公开(公告)日：2021-10-07
申请号：US17351393
申请日：2021-06-18
发明人： Jingyun Zhang , Ruilong Xie , Alexander Reznicek , Bruce B. Doris
IPC分类号： H01L23/485 , H01L21/8234 , H01L21/768 , H01L29/08 , H01L29/06
摘要： A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.
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