公开(公告)号：US10897225B1

公开(公告)日：2021-01-19

申请号：US16583898

申请日：2019-09-26

申请人： International Business Machines Corporation

发明人： James Strom ,  Matthew James Paschal ,  Bruce George Rudolph ,  Daniel M. Dreps

IPC分类号： H03B5/06 ,  H03L7/14 ,  G01R31/28 ,  G06F1/04 ,  H03K23/58 ,  H03K5/19

摘要： A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

公开(公告)号：US20230035405A1

公开(公告)日：2023-02-02

申请号：US17386043

申请日：2021-07-27

申请人： International Business Machines Corporation

发明人： Matthew James Paschal ,  Daniel M. Dreps ,  Glen A. Wiedemeier ,  Bruce George Rudolph ,  James Strom

IPC分类号： G06F1/08 ,  G06F1/12

摘要： A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.