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公开(公告)号：US20230139648A1
公开(公告)日：2023-05-04
申请号：US17453354
申请日：2021-11-03
摘要： Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.
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公开(公告)号：US20230095447A1
公开(公告)日：2023-03-30
申请号：US17489751
申请日：2021-09-29
发明人： Ruilong Xie , Julien Frougier , Kangguo Cheng , CHANRO PARK
IPC分类号： H01L29/417 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786
摘要： A semiconductor structure includes a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers. The structure also includes a second source/drain region contacting the semiconductor nanosheet and extending from the top of the nanosheet stack down through the BDI to the substrate. Accordingly, the nanosheet stack also includes second inner spacers in the nanosheet stack adjacent to the second source/drain region and separating the second source/drain region from the gate stack layers.
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公开(公告)号：US20230090755A1
公开(公告)日：2023-03-23
申请号：US17481198
申请日：2021-09-21
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532
摘要： A dielectric layer is located on top of and in contact with a substrate. A conductive line located within the dialectic layer. A barrier layer on top of an in contact with the dielectric layer. The barrier layer is below the conductive line. A liner layer on top of and in contact with the barrier layer and below and in contact with the conductive line. A metal liner on top of and in contact with the conductive line. A capping layer on top of and in contact with the dielectric layer, the barrier layer, the liner layer, and the metal liner.
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公开(公告)号：US20230090346A1
公开(公告)日：2023-03-23
申请号：US17482928
申请日：2021-09-23
发明人： Ruilong Xie , Julien Frougier , Kangguo Cheng , JUNTAO LI , CHANRO PARK
IPC分类号： H01L27/06 , H01L27/088 , H01L21/822 , H01L21/8234 , H01L29/66
摘要： Stacked FET devices having independent and shared gate contacts are provided. In one aspect of the invention, a stacked FET device includes: a bottom-level FET(s) having a bottom-level FET gate; a top-level FET(s) having a top-level FET gate, wherein an upper portion of the bottom-level FET gate is adjacent to the top-level FET gate; a dielectric sidewall spacer in between the upper portion of the bottom-level FET gate and the top-level FET gate; and a dielectric gate cap disposed over the bottom and top-level FET gates that includes a different dielectric material from the dielectric sidewall spacer. A device having at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.
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5.发明申请公开(公告)号：US20200273979A1
公开(公告)日：2020-08-27
申请号：US16286731
申请日：2019-02-27
发明人： RUILONG XIE , Julien Frougier , CHANRO PARK , Edward Nowak , Yi Qi , Kangguo Cheng , NICOLAS LOUBET
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/16 , H01L29/10 , H01L21/8234 , H01L21/02 , H01L21/324 , H01L27/088
摘要： Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.
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公开(公告)号：US20230125615A1
公开(公告)日：2023-04-27
申请号：US17451686
申请日：2021-10-21
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
摘要： A method of making a semiconductor component includes forming an interconnect in a dielectric layer such that an uppermost surface of the interconnect is substantially coplanar with an uppermost surface of the dielectric layer. The method further includes recessing the dielectric layer such that the uppermost surface of the dielectric layer is lower than the uppermost surface of the interconnect. The method further includes forming spacers in direct contact with the uppermost surface of the recessed dielectric layer such that the spacers are in direct contact with the interconnect. The method further includes recessing the interconnect such that the uppermost surface of the interconnect remains above the uppermost surface of the recessed dielectric layer and is lower than an uppermost surface of the spacers.
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公开(公告)号：US20230116440A1
公开(公告)日：2023-04-13
申请号：US17498718
申请日：2021-10-11
IPC分类号： H01L23/532 , H01L23/522 , H01L21/768 , H01L21/304
摘要： An exemplary semiconductor structure includes a substrate defining a first trench; a first refractory metal liner coating the first trench; a heavy metal liner coating the first refractory metal liner; a copper structure filling the first trench over the heavy metal liner; a generally planar capping dielectric layer on top of the substrate and the copper structure; a low-k dielectric layer on top of the capping dielectric layer, wherein the low-k dielectric layer defines a second trench; a second refractory metal liner coating the second trench; a metal line filling the second refractory metal liner; and a metal via protruding from the metal line.
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公开(公告)号：US20230008763A1
公开(公告)日：2023-01-12
申请号：US17371714
申请日：2021-07-09
发明人： Kangguo Cheng , Ruilong Xie , Julien Frougier , CHANRO PARK
IPC分类号： H01L29/423 , H01L29/66
摘要： A multiple gate dielectrics and dual work-functions field effect transistor (MGO-DWF-FET) is provided on an active region of a semiconductor substrate. The MGO-DWF-FET includes a first functional gate structure including a U-shaped first high-k gate dielectric material layer and a first work-function metal-containing structure, and a laterally adjacent, and contacting, second functional gate structure that includes a U-shaped second high-k gate dielectric material layer and a second work-function metal-containing structure. The first functional gate structure has a gate length that differs from a gate length of the second functional gate structure.
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公开(公告)号：US20210313264A1
公开(公告)日：2021-10-07
申请号：US16840506
申请日：2020-04-06
IPC分类号： H01L23/522 , H01L23/532 , H01L23/528 , H01L21/768
摘要： Interconnect structures and methods for forming the interconnect structures generally include a subtractive etching process to form a fully aligned top via and metal line interconnect structure. The interconnect structure includes a top via and a metal line formed of an alternative metal other than copper or tungsten. A conductive etch stop layer is intermediate the top via and the metal line. The top via is fully aligned to the metal line.
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公开(公告)号：US20210280465A1
公开(公告)日：2021-09-09
申请号：US16813682
申请日：2020-03-09
IPC分类号： H01L21/768 , H01L21/3213 , H01L23/522
摘要： Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.
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