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177 条记录 (耗时 0.031 秒)

    Airgap vertical transistor without structural collapse
    1.
    发明授权
    Airgap vertical transistor without structural collapse 有权

    公开(公告)号：US11637179B2

    公开(公告)日：2023-04-25

    申请号：US17131904

    申请日：2020-12-23

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Chanro Park ,  Juntao Li ,  Ruilong Xie

    IPC分类号： H01L29/06 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L21/764 ,  H01L21/762 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

    摘要： Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.

    LINE FORMATION WITH CUT-FIRST TIP DEFINITION
    4.
    发明申请
    LINE FORMATION WITH CUT-FIRST TIP DEFINITION 有权

    公开(公告)号：US20230090983A1

    公开(公告)日：2023-03-23

    申请号：US17482939

    申请日：2021-09-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Chanro Park ,  Koichi Motoyama ,  Hsueh-Chung Chen ,  Yann Mignot

    IPC分类号： H01L21/768 ,  H01L21/306

    摘要： Semiconductor devices and methods of forming conductive lines in the same include forming a cut region in a first dielectric layer, the cut region having a first width. A second dielectric plug is formed in the cut region. A mask is formed, over the first dielectric layer, that defines at least one trench region that crosses the second dielectric plug, with the at least one trench region having a second width that is smaller than the first width. Material from the first dielectric layer in the trench regions is etched away, using a selective anisotropic etch that leaves the second dielectric plug in place, to form trenches in the first dielectric layer. Conductive material is deposited in the trenches to form conductive lines that are separated by the second dielectric plug.

    SEMICONDUCTOR STRUCTURES WITH POWER RAIL DISPOSED UNDER ACTIVE GATE
    5.
    发明申请
    SEMICONDUCTOR STRUCTURES WITH POWER RAIL DISPOSED UNDER ACTIVE GATE 有权

    公开(公告)号：US20230087690A1

    公开(公告)日：2023-03-23

    申请号：US17479966

    申请日：2021-09-20

    申请人： International Business Machines Corporation

    发明人： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

    IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L27/12 ,  H01L23/535 ,  H01L29/66

    摘要： Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.

    Bi metal subtractive etch for trench and via formation
    7.
    发明授权
    Bi metal subtractive etch for trench and via formation 有权

    公开(公告)号：US11328954B2

    公开(公告)日：2022-05-10

    申请号：US16817988

    申请日：2020-03-13

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Yann Mignot ,  Chanro Park ,  Chih-Chao Yang ,  Injo Ok ,  Hsueh-Chung Chen

    IPC分类号： H01L21/768

    摘要： Embodiments of the present invention disclose a method forming a via and a trench. By utilizing a first etching process, a first metal layer of a multi-layered device to form a via, wherein the multi-layered device comprises the first metal layer and a second metal layer, wherein the first metal layer is formed directly on top of the second metal layer, wherein the second metal layer acts as an etch stop for the first etching process, wherein the first etching process does not affect the second metal layer. By utilizing a second etching process, the second metal layer of the multi-layered device to form a trench, wherein first metal layer is not affected by the second etching process, wherein the first etching process and the second etching process are two different etching process.

    Using selectively formed cap layers to form self-aligned contacts to source/drain regions
    9.
    发明授权
    Using selectively formed cap layers to form self-aligned contacts to source/drain regions 有权

    公开(公告)号：US11211462B2

    公开(公告)日：2021-12-28

    申请号：US16810114

    申请日：2020-03-05

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  ChoongHyun Lee ,  Kangguo Cheng ,  Ruilong Xie

    IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02

    摘要： A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the plurality of gate structures. In the method, a germanium oxide layer is formed on the plurality of gate structures and on the plurality of source/drain regions, and portions of the germanium oxide layer on the plurality of source/drain regions are converted into a plurality of dielectric layers. The method also includes removing unconverted portions of the germanium oxide layer from the plurality of gate structures, and depositing a plurality of cap layers in place of the removed unconverted portions of the germanium oxide layer. The plurality of dielectric layers are removed, and a plurality of source/drain contacts are formed on the plurality of source/drain regions. The plurality of source/drain contacts are adjacent the plurality of cap layers.

    Nanosheet transistor with inner spacers
    10.
    发明授权
    Nanosheet transistor with inner spacers 有权

    公开(公告)号：US11183561B2

    公开(公告)日：2021-11-23

    申请号：US16735972

    申请日：2020-01-07

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Ruilong Xie ,  Chanro Park ,  Juntao Li

    IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/84 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    摘要： A method includes forming a stacked nanosheet structure on a semiconductor substrate. The stacked nanosheet structure includes a plurality of alternating sacrificial nanosheets and channel nanosheets. The method further includes forming a dummy gate structure about the stacked nanosheet structure. The method also includes removing outer surface regions of the sacrificial nanosheets to define an at least partial recess at each outer surface region and forming an inner spacer within each of the at least partial recesses. The method also includes forming an isolation layer adjacent at least outer surface regions of at least the channel nanosheets. The method further includes forming a source region and a drain region about the stacked nanosheet structure. The method also includes removing the sacrificial nanosheets through an etching process whereby the isolation layer and the inner spacers isolates the source and drain regions from the etching process.