-
公开(公告)号：US20240407178A1
公开(公告)日：2024-12-05
申请号：US18205727
申请日：2023-06-05
Applicant: International Business Machines Corporation
Inventor： Guy M. Cohen , Cheng-Wei Cheng , Matthew Joseph BrightSky , Daniel Piatek
Abstract: A phase-change memory cell includes an insulating layer; a first electrode embedded in the insulating layer, wherein an outer end of the first electrode is locally flush with an outer surface of the insulating layer; a second electrode, larger than the first electrode, and spaced from the first electrode; a compositionally homogenous crystalline phase change material layer; and a highly oriented seed layer. A crystal structure of the homogenous phase change material layer is correlated with a crystal structure of the highly oriented seed layer. The compositionally homogenous phase change material layer and the highly oriented seed layer are located at least partially between the first and second electrodes.
-
公开(公告)号：US20240196766A1
公开(公告)日：2024-06-13
申请号：US18063189
申请日：2022-12-08
Applicant: International Business Machines Corporation
Inventor： Matthew Joseph BrightSky , Cheng-Wei Cheng , Guy M. Cohen , Robert L. Bruce , Asit Ray , Wanki Kim
IPC: H01L47/00
CPC classification number: H01L45/1246 , H01L45/06 , H01L45/144
Abstract: An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.
-
公开(公告)号：US20230180636A1
公开(公告)日：2023-06-08
申请号：US17457750
申请日：2021-12-06
Applicant: International Business Machines Corporation
CPC classification number: H01L45/1616 , H01L45/06 , H01L45/1675 , H01L45/145 , H01L45/1253 , H01L45/1691 , H01L27/2463
Abstract: A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.
-
公开(公告)号：US11563173B2
公开(公告)日：2023-01-24
申请号：US16735759
申请日：2020-01-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Heng Wu , Ruilong Xie , Nanbo Gong , Cheng-Wei Cheng
Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.
-
公开(公告)号：US20220209113A1
公开(公告)日：2022-06-30
申请号：US17136107
申请日：2020-12-29
Applicant: International Business Machines Corporation
Inventor： Cheng-Wei Cheng , Huai-Yu Cheng , I-Ting Kuo , Robert L. Bruce , Martin Michael Frank , Hiroyuki Miyazoe
Abstract: A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.
-
公开(公告)号：US10998420B2
公开(公告)日：2021-05-04
申请号：US15945305
申请日：2018-04-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kuen-Ting Shiu , Tak H. Ning , Jeng-Bang Yau , Cheng-Wei Cheng , Ko-Tao Lee
IPC: H01L29/66 , H01L29/737 , H01L21/308 , H01L29/06 , H01L21/306 , H01L29/205
Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
-
7.发明申请
公开(公告)号：US20190140424A1
公开(公告)日：2019-05-09
申请号：US16239657
申请日：2019-01-04
Applicant: International Business Machines Corporation
Inventor： Cheng-Wei Cheng , Effendi Leobandung , Ning Li , Devendra K. Sadana , Kuen-Ting Shiu
IPC: H01S5/183 , H01L31/18 , H01S5/02 , H01L31/0232 , H01L31/0304 , H01L33/30 , H01L33/12 , H01L33/10 , H01L33/00 , H01L31/105 , H01S5/187 , H01S5/343 , H01L33/02
CPC classification number: H01S5/18377 , H01L31/02327 , H01L31/0304 , H01L31/105 , H01L31/1852 , H01L33/0012 , H01L33/0066 , H01L33/025 , H01L33/105 , H01L33/12 , H01L33/30 , H01S5/021 , H01S5/0218 , H01S5/0262 , H01S5/18361 , H01S5/187 , H01S5/3432 , H01S5/34366
Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8
-
8.发明申请
公开(公告)号：US20180277367A1
公开(公告)日：2018-09-27
申请号：US15467265
申请日：2017-03-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Stephen W. Bedell , Cheng-Wei Cheng , Kunal Mukherjee , John A. Ott , Devendra K. Sadana , Brent A. Wacaser
IPC: H01L21/02 , H01L29/04 , H01L21/306 , H01L21/3065
CPC classification number: H01L21/02694 , H01L21/02488 , H01L21/02513 , H01L21/02538 , H01L21/02546 , H01L21/02609 , H01L21/02614 , H01L21/02664 , H01L21/02667 , H01L21/30617 , H01L21/3065 , H01L29/04
Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
-
公开(公告)号：US09947755B2
公开(公告)日：2018-04-17
申请号：US14870794
申请日：2015-09-30
Applicant: International Business Machines Corporation
Inventor： Kevin K. Chan , Cheng-Wei Cheng , Jack Oon Chu , Yanning Sun , Jeng-Bang Yau
IPC: H01L29/41 , H01L29/20 , H01L29/66 , H01L29/78 , H01L29/417 , H01L29/201 , H01L21/283 , H01L21/3213 , H01L21/3205 , H01L21/02 , H01L21/285 , H01L29/08 , H01L29/45
CPC classification number: H01L29/41783 , H01L21/02546 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02631 , H01L21/283 , H01L21/28575 , H01L21/32051 , H01L21/32134 , H01L29/0847 , H01L29/20 , H01L29/201 , H01L29/452 , H01L29/665 , H01L29/66522 , H01L29/66795 , H01L29/78 , H01L29/7835
Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source including III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer including silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer including transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer including transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
-
公开(公告)号：US09947533B2
公开(公告)日：2018-04-17
申请号：US15343078
申请日：2016-11-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Cheng-Wei Cheng , Jeehwan Kim , John A. Ott , Devendra K. Sadana
IPC: H01L21/20 , H01L21/027 , H01L21/02 , H01L21/308
CPC classification number: H01L21/0274 , H01L21/02378 , H01L21/02444 , H01L21/02485 , H01L21/02527 , H01L21/0254 , H01L21/02612 , H01L21/02639 , H01L21/02642 , H01L21/308
Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
