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公开(公告)号:US11437571B2
公开(公告)日:2022-09-06
申请号:US16451178
申请日:2019-06-25
发明人: Wanki Kim , Fabio Carta , Chung H. Lam , Robert L. Bruce
摘要: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.
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公开(公告)号:US20200075097A1
公开(公告)日:2020-03-05
申请号:US16679782
申请日:2019-11-11
发明人: Chung H. Lam , Scott C. Lewis , Thomas M. Maffitt , Jack Morrish
摘要: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
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公开(公告)号:US10424375B2
公开(公告)日:2019-09-24
申请号:US15812213
申请日:2017-11-14
发明人: Chung H. Lam , Scott C. Lewis , Thomas M. Maffitt , Jack Morrish
摘要: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
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公开(公告)号:US20180205017A1
公开(公告)日:2018-07-19
申请号:US15408392
申请日:2017-01-17
发明人: Robert L. Bruce , Fabio Carta , Wanki Kim , Chung H. Lam
CPC分类号: H01L45/1683 , H01L27/2409 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144
摘要: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.
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公开(公告)号:US09583624B1
公开(公告)日:2017-02-28
申请号:US14865276
申请日:2015-09-25
发明人: Chung H. Lam , Chung-hsun Lin , Darsen D. Lu , Philip J. Oldiges
CPC分类号: H01L29/785 , H01L21/02532 , H01L21/30604 , H01L21/3081 , H01L21/31111 , H01L29/0847 , H01L29/6653 , H01L29/66553 , H01L29/66795
摘要: A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.
摘要翻译: 场效晶体管器件包括半导体衬底,布置在半导体衬底上的掺杂源极层,布置在掺杂源极层上的绝缘体层,布置在绝缘体层上的鳍片,从掺杂源层延伸的源极区域延伸部分和 通过所述鳍片,布置在所述鳍片的沟道区域上并且邻近所述源极区域延伸部分的栅极堆叠;布置在所述鳍片上邻近所述栅极叠层的漏极区域; 所述漏极区域具有刻度的掺杂浓度。
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公开(公告)号:US09502107B2
公开(公告)日:2016-11-22
申请号:US14834885
申请日:2015-08-25
CPC分类号: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2013/0066 , G11C2013/0078 , G11C2013/0092
摘要: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
摘要翻译: 这里公开了用于多位相变存储器的结构和方法。 一种方法包括建立在写入周期上递增地斜坡的写参考电压。 写参考电压的增量对应于多位相变存储器的存储单元的离散电阻状态。
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公开(公告)号:US20160203858A1
公开(公告)日:2016-07-14
申请号:US14596223
申请日:2015-01-14
发明人: SangBum Kim , Chung H. Lam
CPC分类号: G11C11/54 , G06N3/049 , G06N3/063 , G06N3/088 , G11C11/5678 , G11C13/0002 , G11C13/0004
摘要: A neuromorphic memory circuit including a programmable resistive memory element, an axon LIF line to transmit an axon LIF pulse, and a dendrite LIF line to build up a dendrite LIF charge over time. A first transistor provides a discharge path for the dendrite LIF charge through the programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. An axon STDP line transmits an axon STDP pulse. The axon STDP pulse is longer than the axon LIF pulse. A dendrite STDP line is configured to transmit a dendrite STDP pulse after voltage at the dendrite LIF line falls below a threshold voltage. A second transistor is coupled to the axon STDP line and the programmable resistive memory element. The second transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
摘要翻译: 包括可编程电阻性存储器元件,用于透射轴突LIF脉冲的轴突LIF线和枝晶LIF线的神经形态记忆电路,以随时间建立枝晶LIF电荷。 当轴突LIF线透射轴突LIF脉冲时,第一晶体管提供通过可编程电阻存储元件的枝晶LIF电荷的放电路径。 轴突STDP线传输轴突STDP脉冲。 轴突STDP脉冲长于轴突LIF脉冲。 树枝状STDP线被配置为在枝晶LIF线处的电压低于阈值电压之后传输枝晶STDP脉冲。 第二晶体管耦合到轴突STDP线和可编程电阻存储元件。 当轴突STDP线透射轴突STDP脉冲时,第二晶体管为通过可编程电阻式存储器元件的枝晶STDP脉冲提供电路径。
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公开(公告)号:US09245619B2
公开(公告)日:2016-01-26
申请号:US14197201
申请日:2014-03-04
发明人: Kyu-hyoun Kim , SangBum Kim , Chung H. Lam
CPC分类号: G11C13/004 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1693 , G11C11/5607 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0069
摘要: Devices and methods for accurate reading of data in memory technology prone to drifting memory characteristics. An example device includes a memory array for storing data, and a memory buffer for storing a subset of the data in the memory array. A memory controller is configured to read data from the memory buffer if the data was written to the memory array before a predetermined duration of time, and to read the data from the memory array if the data is at least one of not valid or not available at the memory buffer.
摘要翻译: 用于准确读取存储器技术中的数据的装置和方法易于漂移记忆特性。 示例性设备包括用于存储数据的存储器阵列和用于存储数据在存储器阵列中的子集的存储器缓冲器。 如果在预定持续时间之前将数据写入存储器阵列,则存储器控制器被配置为从存储器缓冲器读取数据,并且如果数据是不可用或不可用的至少一个,则从存储器阵列读取数据 在内存缓冲区。
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公开(公告)号:US09219231B2
公开(公告)日:2015-12-22
申请号:US14180344
申请日:2014-02-13
发明人: Chung H. Lam , Alejandro G. Schrott
IPC分类号: H01L45/00
CPC分类号: H01L45/1253 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/141 , H01L45/1683
摘要: An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.
摘要翻译: 示例性实施例是一种相变存储单元,其包括在底部电极之上的通孔内承载的底部电极和相变材料。 表面活性剂层沉积在底部电极上方。 表面活性剂层包括配置成降低相变材料和通孔表面之间的界面力的表面活性剂。
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公开(公告)号:US20150348844A1
公开(公告)日:2015-12-03
申请号:US14288600
申请日:2014-05-28
发明人: Matthew J. BrightSky , Jin Cai , SangBum Kim , Chung H. Lam , Tak H. Ning
IPC分类号: H01L21/8222 , H01L27/22 , H01L27/24
CPC分类号: H01L21/8222 , H01L27/1022 , H01L27/226 , H01L27/2445 , H01L29/66234
摘要: A method of manufacturing a bipolar junction transistor (BJT) array may include forming a substrate of doped silicon and forming a plurality of BJTs on the substrate. Each of the BJTs may have a first region and a second region sandwiching a base region vertically. The first region may be in contact with the substrate, where the BJTs are formed in a first row and a second row. The first row and the second row may each have BJTs separated from one another by a word line distance and the first row and second row may be separated by a bit line distance. A plurality of word line contacts may be formed laterally enclosing and electrically connected to each base region of the BJTs. The word line contacts may have a lateral thickness more than one half the word line distance and less than one half the bit line distance.
摘要翻译: 制造双极结型晶体管(BJT)阵列的方法可以包括形成掺杂硅的衬底并在衬底上形成多个BJT。 每个BJT可以具有第一区域和第二区域,垂直地夹着基底区域。 第一区域可以与基底接触,其中BJT形成在第一行和第二行中。 第一行和第二行可以各自具有通过字线距离彼此分开的BJT,并且第一行和第二行可以被位线距离分隔。 多个字线触点可以横向包围并电连接到BJT的每个基区。 字线触点可以具有大于字线距离的一半的横向厚度,并且小于位线距离的一半。
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