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    Back end of line embedded RRAM structure with low forming voltage
    1.
    发明授权
    Back end of line embedded RRAM structure with low forming voltage 有权

    公开(公告)号：US12144271B2

    公开(公告)日：2024-11-12

    申请号：US17444841

    申请日：2021-08-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Oleg Gluschenkov ,  Alexander Reznicek ,  Youngseok Kim ,  Injo Ok ,  Soon-Cheon Seo

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

    VERTICAL MAGNETIC TUNNEL JUNCTION DEVICE
    2.
    发明公开
    VERTICAL MAGNETIC TUNNEL JUNCTION DEVICE 审中-公开

    公开(公告)号：US20240237544A1

    公开(公告)日：2024-07-11

    申请号：US18150816

    申请日：2023-01-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kevin W. Brew ,  Ching-Tzu Chen ,  Timothy Mathew Philip ,  JIN PING HAN ,  Injo Ok

    IPC: H10N50/10 ,  H01L23/528 ,  H10N50/01

    CPC classification number: H10N50/10 ,  H01L23/5283 ,  H10N50/01

    Abstract: Embodiments of present invention provide a vertical magnetic tunnel junction (MTJ) structure. The structure includes an L-shaped MTJ stack including an L-shaped reference layer conformally on an L-shaped performance enhancing layer; an L-shaped tunnel barrier layer conformally on the L-shaped reference layer; and an L-shaped free layer conformally on the L-shaped tunnel barrier layer, where a vertical portion of the L-shaped MTJ stack is adjacent to a sidewall of a metal stud, the metal stud being directly on top of a metal wire in a dielectric layer. The structure further includes a first and a second electrode contacting a horizontal portion and a vertical portion of the L-shaped MTJ stack. A method of forming the same is also provided.

    ANTENNA ASSISTED RERAM FORMATION
    4.
    发明公开
    ANTENNA ASSISTED RERAM FORMATION 审中-公开

    公开(公告)号：US20230309421A1

    公开(公告)日：2023-09-28

    申请号：US18205208

    申请日：2023-06-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Youngseok Kim ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    CPC classification number: H10N70/011 ,  H10B63/20 ,  H10N70/24 ,  H10N70/257 ,  H10N70/841

    Abstract: A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

    Resistive memory array
    7.
    发明授权
    Resistive memory array 有权

    公开(公告)号：US11588103B2

    公开(公告)日：2023-02-21

    申请号：US17104405

    申请日：2020-11-25

    Applicant: International Business Machines Corporation

    Inventor： Youngseok Kim ,  Choonghyun Lee ,  Timothy Mathew Philip ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

    BACK END OF LINE EMBEDDED RRAM STRUCTURE WITH LOW FORMING VOLTAGE
    8.
    发明申请
    BACK END OF LINE EMBEDDED RRAM STRUCTURE WITH LOW FORMING VOLTAGE 有权

    公开(公告)号：US20230051052A1

    公开(公告)日：2023-02-16

    申请号：US17444841

    申请日：2021-08-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Oleg Gluschenkov ,  Alexander Reznicek ,  Youngseok Kim ,  Injo Ok ,  Soon-Cheon Seo

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

    SETTING AN UPPER BOUND ON RRAM RESISTANCE
    9.
    发明申请
    SETTING AN UPPER BOUND ON RRAM RESISTANCE 有权

    公开(公告)号：US20220223205A1

    公开(公告)日：2022-07-14

    申请号：US17147401

    申请日：2021-01-12

    Applicant: International Business Machines Corporation

    Inventor： Youngseok Kim ,  Soon-Cheon Seo ,  Choonghyun Lee ,  Injo Ok ,  Alexander Reznicek

    IPC: G11C13/00 ,  H01L45/00

    Abstract: An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; and a plurality of resistive random-access memory cells located at the plurality of grid points. Each of the resistive random-access memory cells includes a top metal coupled to one of: a corresponding one of the word lines and a corresponding one of the bit lines; a bottom metal coupled to another one of: the corresponding one of the word lines and the corresponding one of the bit lines; a dielectric sandwiched between the top metal and the bottom metal; and a high-resistance semiconductive spacer electrically connecting the top metal and the bottom metal in parallel with the dielectric.

    RESISTIVE MEMORY ARRAY
    10.
    发明申请
    RESISTIVE MEMORY ARRAY 有权

    公开(公告)号：US20220165947A1

    公开(公告)日：2022-05-26

    申请号：US17104405

    申请日：2020-11-25

    Applicant: International Business Machines Corporation

    Inventor： Youngseok Kim ,  Choonghyun Lee ,  Timothy Mathew Philip ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

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